Add SPI buffer read/write logic

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2629 42af7a65-404d-4744-a932-0658087f49c3

2 files changed, 187 insertions, 6 deletions

diff --git a/nuttx/drivers/net/enc28j60.c b/nuttx/drivers/net/enc28j60.c
index 87ae285f6..ad828c43b 100755
--- a/nuttx/drivers/net/enc28j60.c
+++ b/nuttx/drivers/net/enc28j60.c
@@ -163,6 +163,9 @@ static inline uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi);
 static uint8_t enc28j60_select(FAR struct spi_dev_s *spi);
 static uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi);
 #endif
+
+/* SPI control register access */
+
 static uint8_t enc28j60_rdglobal2(FAR struct enc28j60_driver_s *priv,
          uint8_t cmd);
 static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
@@ -173,6 +176,13 @@ static uint8_t enc28j60_rdbank(FAR struct enc28j60_driver_s *priv,
 static uint8_t enc28j60_rdphymac(FAR struct enc28j60_driver_s *priv,
          uint8_t ctrlreg);
 
+/* SPI buffer transfers */
+
+static void enc28j60_rdbuffer(FAR struct enc28j60_driver_s *priv,
+         FAR uint8_t *buffer, size_t buflen);
+static void enc28j60_wrbuffer(FAR struct enc28j60_driver_s *priv,
+         FAR const uint8_t *buffer, size_t buflen);
+
 /* Common TX logic */
 
 static int  enc28j60_transmit(FAR struct enc28j60_driver_s *priv);
@@ -240,7 +250,7 @@ static inline uint8_t enc28j60_select(FAR struct spi_dev_s *spi)
 #else
 static uint8_t enc28j60_select(FAR struct spi_dev_s *spi)
 {
-  /* Select ENC2J60 chip (locking the SPI bus in case there are multiple
+  /* Select ENC28J60 chip (locking the SPI bus in case there are multiple
    * devices competing for the SPI bus
    */
 
@@ -302,7 +312,7 @@ static uint8_t enc28j60_rdglobal2(FAR struct enc28j60_driver_s *priv,
   DEBUGASSERT(priv && priv->spi);
   spi = priv->spi;
 
-  /* Select ENC2J60 chip */
+  /* Select ENC28J60 chip */
 
   enc28j60_select(spi);
 
@@ -333,7 +343,7 @@ static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
   DEBUGASSERT(priv && priv->spi);
   spi = priv->spi;
 
-  /* Select ENC2J60 chip */
+  /* Select ENC28J60 chip */
 
   enc28j60_select(spi);
 
@@ -351,6 +361,72 @@ static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
 }
 
 /****************************************************************************
+ * Function: enc28j60_rdbuffer
+ *
+ * Description:
+ *   Read a buffer of data.
+ *
+ ****************************************************************************/
+
+static void enc28j60_rdbuffer(FAR struct enc28j60_driver_s *priv,
+                              FAR uint8_t *buffer, size_t buflen)
+{
+  FAR struct spi_dev_s *spi;
+
+  DEBUGASSERT(priv && priv->spi);
+  spi = priv->spi;
+
+  /* Select ENC28J60 chip */
+
+  enc28j60_select(spi);
+
+  /* Send the read buffer memory command (ignoring the response) */
+
+  (void)SPI_SEND(spi, ENC28J60_RBM);
+ 
+  /* Then read the buffer data */
+
+  SPI_RECVBLOCK(spi, buffer, buflen);
+
+  /* De-select ENC28J60 chip. */
+
+  enc28j60_deselect(spi);
+}
+
+/****************************************************************************
+ * Function: enc28j60_wrbuffer
+ *
+ * Description:
+ *   Write a buffer of data.
+ *
+ ****************************************************************************/
+
+static void enc28j60_wrbuffer(FAR struct enc28j60_driver_s *priv,
+                              FAR const uint8_t *buffer, size_t buflen)
+{
+  FAR struct spi_dev_s *spi;
+
+  DEBUGASSERT(priv && priv->spi);
+  spi = priv->spi;
+
+  /* Select ENC28J60 chip */
+
+  enc28j60_select(spi);
+
+  /* Send the write buffer memory command (ignoring the response) */
+
+  (void)SPI_SEND(spi, ENC28J60_WBM);
+ 
+  /* Then send the buffer */
+
+  SPI_SNDBLOCK(spi, buffer, buflen);
+
+  /* De-select ENC28J60 chip. */
+
+  enc28j60_deselect(spi);
+}
+
+/****************************************************************************
  * Function: enc28j60_setbank
  *
  * Description:
@@ -401,7 +477,7 @@ static uint8_t enc28j60_rdbank(FAR struct enc28j60_driver_s *priv,
   DEBUGASSERT(priv && priv->spi);
   spi = priv->spi;
 
-  /* Select ENC2J60 chip */
+  /* Select ENC28J60 chip */
 
   enc28j60_select(spi);
 
@@ -438,7 +514,7 @@ static uint8_t enc28j60_rdphymac(FAR struct enc28j60_driver_s *priv,
   DEBUGASSERT(priv && priv->spi);
   spi = priv->spi;
 
-  /* Select ENC2J60 chip */
+  /* Select ENC28J60 chip */
 
   enc28j60_select(spi);
 
@@ -476,7 +552,7 @@ static void enc28j60_wrbank(FAR struct enc28j60_driver_s *priv,
   DEBUGASSERT(priv && priv->spi);
   spi = priv->spi;
 
-  /* Select ENC2J60 chip */
+  /* Select ENC28J60 chip */
 
   enc28j60_select(spi);
 
diff --git a/nuttx/drivers/net/enc28j60.h b/nuttx/drivers/net/enc28j60.h
index a3840128b..9496ee9f7 100755
--- a/nuttx/drivers/net/enc28j60.h
+++ b/nuttx/drivers/net/enc28j60.h
@@ -101,6 +101,111 @@
 #define GETADDR(a)          ((a) & ENC28J60_ADDR_MASK)
 #define GETBANK(a)          (((a) >> ENC28J60_BANK_SHIFT) & 3)
 
+/* Bank 0 Control Register Addresses */
+
+#define ERDPTL      REGADDR(0x00, 0) /* Read Pointer Low Byte (ERDPT<7:0> */
+#define ERDPTH      REGADDR(0x01, 0) /* Read Pointer High Byte (ERDPT<12:8>) */
+#define EWRPTL      REGADDR(0x02, 0) /* Write Pointer Low Byte (EWRPT<7:0>) */
+#define EWRPTH      REGADDR(0x03, 0) /* Write Pointer High Byte (EWRPT<12:8>) */
+#define ETXSTL      REGADDR(0x04, 0) /* TX Start Low Byte (ETXST<7:0>) */
+#define ETXSTH      REGADDR(0x05, 0) /* TX Start High Byte (ETXST<12:8>) */
+#define ETXNDL      REGADDR(0x06, 0) /* TX End Low Byte (ETXND<7:0>) */
+#define ETXNDH      REGADDR(0x07, 0) /* TX End High Byte (ETXND<12:8>) */
+#define ERXSTL      REGADDR(0x08, 0) /* RX Start Low Byte (ERXST<7:0>) */
+#define ERXSTH      REGADDR(0x09, 0) /* RX Start High Byte (ERXST<12:8>) */
+#define ERXNDL      REGADDR(0x0a, 0) /* RX End Low Byte (ERXND<7:0>) */
+#define ERXNDH      REGADDR(0x0b, 0) /* RX End High Byte (ERXND<12:8>) */
+#define ERXRDPTL    REGADDR(0x0c, 0) /* RX RD Pointer Low Byte (ERXRDPT<7:0>) */
+#define ERXRDPTH    REGADDR(0x0d, 0) /* RX RD Pointer High Byte (ERXRDPT<12:8>) */
+#define ERXWRPTL    REGADDR(0x0e, 0) /* RX WR Pointer Low Byte (ERXWRPT<7:0>) */
+#define ERXWRPTH    REGADDR(0x0f, 0) /* RX WR Pointer High Byte (ERXWRPT<12:8>) */
+#define EDMASTL     REGADDR(0x10, 0) /* DMA Start Low Byte (EDMAST<7:0>) */
+#define EDMASTH     REGADDR(0x11, 0) /* DMA Start High Byte (EDMAST<12:8>) */
+#define EDMANDL     REGADDR(0x12, 0) /* DMA End Low Byte (EDMAND<7:0>) */
+#define EDMANDH     REGADDR(0x13, 0) /* DMA End High Byte (EDMAND<12:8>) */
+#define EDMADSTL    REGADDR(0x14, 0) /* DMA Destination Low Byte (EDMADST<7:0>) */
+#define EDMADSTH    REGADDR(0x15, 0) /* DMA Destination High Byte (EDMADST<12:8>) */
+#define EDMACSL     REGADDR(0x16, 0) /* DMA Checksum Low Byte (EDMACS<7:0>) */
+#define EDMACSH     REGADDR(0x17, 0) /* DMA Checksum High Byte (EDMACS<15:8>) */
+                                     /* 0x18-0x1a: Reserved */
+                                     /* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
+/* Bank 1 Control Register Addresses */
+
+#define EHT0        REGADDR(0x00, 1) /* Hash Table Byte 0 (EHT<7:0>) */
+#define EHT1        REGADDR(0x01, 1) /* Hash Table Byte 1 (EHT<15:8>) */
+#define EHT2        REGADDR(0x02, 1) /* Hash Table Byte 2 (EHT<23:16>) */
+#define EHT3        REGADDR(0x03, 1) /* Hash Table Byte 3 (EHT<31:24>) */
+#define EHT4        REGADDR(0x04, 1) /* Hash Table Byte 4 (EHT<39:32>) */
+#define EHT5        REGADDR(0x05, 1) /* Hash Table Byte 5 (EHT<47:40>) */
+#define EHT6        REGADDR(0x06, 1) /* Hash Table Byte 6 (EHT<55:48>) */
+#define EHT7        REGADDR(0x07, 1) /* Hash Table Byte 7 (EHT<63:56>) */
+#define EPMM0       REGADDR(0x08, 1) /* Pattern Match Mask Byte 0 (EPMM<7:0>) */
+#define EPMM1       REGADDR(0x09, 1) /* Pattern Match Mask Byte 1 (EPMM<15:8>) */
+#define EPMM2       REGADDR(0x0a, 1) /* Pattern Match Mask Byte 2 (EPMM<23:16>) */
+#define EPMM3       REGADDR(0x0b, 1) /* Pattern Match Mask Byte 3 (EPMM<31:24>) */
+#define EPMM4       REGADDR(0x0c, 1) /* Pattern Match Mask Byte 4 (EPMM<39:32>) */
+#define EPMM5       REGADDR(0x0d, 1) /* Pattern Match Mask Byte 5 (EPMM<47:40>) */
+#define EPMM6       REGADDR(0x0e, 1) /* Pattern Match Mask Byte 6 (EPMM<55:48>) */
+#define EPMM7       REGADDR(0x0f, 1) /* Pattern Match Mask Byte 7 (EPMM<63:56>) */
+#define EPMCSL      REGADDR(0x10, 1) /* Pattern Match Checksum Low Byte (EPMCS<7:0>) */
+#define EPMCSH      REGADDR(0x11, 1) /* Pattern Match Checksum High Byte (EPMCS<15:0>) */
+                                     /* 0x12-0x13: Reserved */
+#define EPMOL       REGADDR(0x14, 1) /* Pattern Match Offset Low Byte (EPMO<7:0>) */
+#define EPMOH       REGADDR(0x15, 1) /* Pattern Match Offset High Byte (EPMO<12:8>) */
+                                     /* 0x16-0x17: Reserved */
+#define ERXFCON     REGADDR(0x18, 1) /* Receive Filter Configuration */
+#define EPKTCNT     REGADDR(0x19, 1) /* Ethernet Packet Count */
+                                     /* 0x1a: Reserved */
+                                     /* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
+/* Bank 2 Control Register Addresses */
+
+#define MACON1      REGADDR(0x00, 2) /* MAC control 1 */
+#define MACON2      REGADDR(0x01, 2) /* MAC control 2 */
+#define MACON3      REGADDR(0x02, 2) /* MAC control 3 */
+#define MACON4      REGADDR(0x03, 2) /* MAC control 4 */
+#define MABBIPG     REGADDR(0x04, 2) /* Back-to-Back Inter-Packet Gap (BBIPG<6:0>) */
+                                     /* 0x05: Reserved */
+#define MAIPGL      REGADDR(0x06, 2) /* Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) */
+#define MAIPGH      REGADDR(0x07, 2) /* Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) */
+#define MACLCON1    REGADDR(0x08, 2) /* MAC Collision Control 1 */
+#define MACLCON2    REGADDR(0x09, 2) /* MAC Collision Control 2 */
+#define MAMXFLL     REGADDR(0x0a, 2) /* Maximum Frame Length Low Byte (MAMXFL<7:0>) */
+#define MAMXFLH     REGADDR(0x0b, 2) /* Maximum Frame Length High Byte (MAMXFL<15:8>) */
+                                     /* 0x0c-0x11: Reserved */
+#define MICMD       REGADDR(0x12, 2) /* MII Command Register */
+                                     /* 0x13: Reserved */
+#define MIREGADR    REGADDR(0x14, 2) /* MII Register Address */
+                                     /* 0x15: Reserved */
+#define MIWRL       REGADDR(0x16, 2) /* MII Write Data Low Byte (MIWR<7:0>) */
+#define MIWRH       REGADDR(0x17, 2) /* MII Write Data High Byte (MIWR<15:8>) */
+#define MIRDL       REGADDR(0x18, 2) /* MII Read Data Low Byte (MIRD<7:0>) */
+#define MIRDH       REGADDR(0x19, 2) /* MII Read Data High Byte(MIRD<15:8>) */
+                                     /* 0x1a: Reserved */
+                                     /* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
+/* Bank 3 Control Register Addresses */
+
+#define MAADR5      REGADDR(0x00, 3) /* MAC Address Byte 5 (MAADR<15:8>) */
+#define MAADR6      REGADDR(0x01, 3) /* MAC Address Byte 6 (MAADR<7:0>) */
+#define MAADR3      REGADDR(0x02, 3) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */
+#define MAADR4      REGADDR(0x03, 3) /* MAC Address Byte 4 (MAADR<23:16>) */
+#define MAADR1      REGADDR(0x04, 3) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */
+#define MAADR2      REGADDR(0x05, 3) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte  */
+#define EBSTSD      REGADDR(0x06, 3) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */
+#define EBSTCON     REGADDR(0x07, 3) /* Built-in Self-Test Control */
+#define EBSTCSL     REGADDR(0x08, 3) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */
+#define EBSTCSH     REGADDR(0x09, 3) /* Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) */
+#define MISTAT      REGADDR(0x0a, 3) /* MII Status Register */
+                                     /* 0x0b-0x11: Reserved */
+#define EREVID      REGADDR(0x12, 3) /* Ethernet Revision ID */
+                                     /* 0x13-0x14: Reserved */
+#define ECOCON      REGADDR(0x15, 3) /* Clock Output Control */
+                                     /* 0x16: Reserved */
+#define EFLOCON     REGADDR(0x17, 3) /* Ethernet Flow Control */
+#define EPAUSL      REGADDR(0x18, 3) /* Pause Timer Value Low Byte (EPAUS<7:0>) */
+#define EPAUSH      REGADDR(0x19, 3) /* Pause Timer Value High Byte (EPAUS<15:8>) */
+                                     /* 0x1a: Reserved */
+                                     /* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
+
 /* Ethernet Interrupt Enable Register Bit Definitions */
 
 #define EIE_RXERIE          (1 << 0) /* Bit 0: Receive Error Interrupt Enable */