diff options
Diffstat (limited to 'nuttx/arch/arm/src/lpc17xx/chip.h')
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip.h | 158 |
1 files changed, 5 insertions, 153 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index 982482017..60dda773d 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -41,159 +41,7 @@ ************************************************************************************/ #include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1767) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 0 /* No USB device controller */ -# define LPC17_NCAN 0 /* No CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1766) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1765) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1764) -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1759) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1758) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1756) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1754) -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1752) -# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */ -# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1751) -# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */ -# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */ -# define LPC17_CPUSRAM_SIZE (8*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#else -# error "Unsupported LPC17xx chip" -#endif +#include <arch/lpc17xx/chip.h> /* Include only the memory map. Other chip hardware files should then include this * file for the proper setup @@ -201,6 +49,10 @@ #include "lpc17_memorymap.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + /* NVIC priority levels *************************************************************/ /* Each priority field holds a priority value, 0-31. The lower the value, the greater * the priority of the corresponding interrupt. The processor implements only |