diff options
Diffstat (limited to 'nuttx/arch/arm/src')
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/Kconfig | 56 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip.h | 158 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c | 3 |
3 files changed, 60 insertions, 157 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/Kconfig b/nuttx/arch/arm/src/lpc17xx/Kconfig index 8acd67595..b7dd7ac34 100644 --- a/nuttx/arch/arm/src/lpc17xx/Kconfig +++ b/nuttx/arch/arm/src/lpc17xx/Kconfig @@ -12,49 +12,101 @@ choice config ARCH_CHIP_LPC1751 bool "LPC1751" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1752 bool "LPC1752" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1754 bool "LPC1754" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1756 bool "LPC1756" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1758 bool "LPC1758" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1759 bool "LPC1759" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1764 bool "LPC1764" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1765 bool "LPC1765" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1766 bool "LPC1766" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1767 bool "LPC1767" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1768 bool "LPC1768" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1769 bool "LPC1769" + select ARCH_FAMILY_LPC176X + +config ARCH_CHIP_LPC1773 + bool "LPC1773" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1774 + bool "LPC1774" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1776 + bool "LPC1776" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1777 + bool "LPC1777" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1778 + bool "LPC1778" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1785 + bool "LPC1785" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1786 + bool "LPC1786" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1787 + bool "LPC1787" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1788 + bool "LPC1788" + select ARCH_FAMILY_LPC178X endchoice config ARCH_FAMILY_LPC175X bool - default y if ARCH_CHIP_LPC1751 || ARCH_CHIP_LPC1752 || ARCH_CHIP_LPC1754 || ARCH_CHIP_LPC1756 || ARCH_CHIP_LPC1758 || ARCH_CHIP_LPC1759 config ARCH_FAMILY_LPC176X bool - default y if ARCH_CHIP_LPC1764 || ARCH_CHIP_LPC1765 || ARCH_CHIP_LPC1766 || ARCH_CHIP_LPC1767 || ARCH_CHIP_LPC1768 || ARCH_CHIP_LPC1769 + +config ARCH_FAMILY_LPC177X + bool + +config ARCH_FAMILY_LPC178X + bool menu "LPC17xx Peripheral Support" diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index 982482017..60dda773d 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -41,159 +41,7 @@ ************************************************************************************/ #include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1767) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 0 /* No USB device controller */ -# define LPC17_NCAN 0 /* No CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1766) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1765) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1764) -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1759) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1758) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1756) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1754) -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1752) -# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */ -# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1751) -# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */ -# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */ -# define LPC17_CPUSRAM_SIZE (8*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#else -# error "Unsupported LPC17xx chip" -#endif +#include <arch/lpc17xx/chip.h> /* Include only the memory map. Other chip hardware files should then include this * file for the proper setup @@ -201,6 +49,10 @@ #include "lpc17_memorymap.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + /* NVIC priority levels *************************************************************/ /* Each priority field holds a priority value, 0-31. The lower the value, the greater * the priority of the corresponding interrupt. The processor implements only diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c index 76c446c7d..db6fbe1f8 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc17xx/lpc17_ssp.c * - * Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -926,4 +926,3 @@ void ssp_flush(FAR struct spi_dev_s *dev) } #endif /* CONFIG_LPC17_SSP0/1 */ - |