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-rw-r--r--nuttx/arch/arm/include/armv7-m/irq.h (renamed from nuttx/arch/arm/include/cortexm3/irq.h)8
-rw-r--r--nuttx/arch/arm/include/armv7-m/syscall.h (renamed from nuttx/arch/arm/include/cortexm3/syscall.h)8
-rw-r--r--nuttx/arch/arm/include/irq.h6
-rw-r--r--nuttx/arch/arm/include/syscall.h4
-rw-r--r--nuttx/arch/arm/src/Makefile8
-rw-r--r--nuttx/arch/arm/src/armv7-m/exc_return.h (renamed from nuttx/arch/arm/src/cortexm3/exc_return.h)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/mpu.h (renamed from nuttx/arch/arm/src/cortexm3/mpu.h)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/nvic.h (renamed from nuttx/arch/arm/src/cortexm3/nvic.h)454
-rw-r--r--nuttx/arch/arm/src/armv7-m/psr.h (renamed from nuttx/arch/arm/src/cortexm3/psr.h)58
-rw-r--r--nuttx/arch/arm/src/armv7-m/svcall.h (renamed from nuttx/arch/arm/src/cortexm3/svcall.h)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_assert.c (renamed from nuttx/arch/arm/src/cortexm3/up_assert.c)2
-rwxr-xr-xnuttx/arch/arm/src/armv7-m/up_blocktask.c (renamed from nuttx/arch/arm/src/cortexm3/up_blocktask.c)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_copystate.c (renamed from nuttx/arch/arm/src/cortexm3/up_copystate.c)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_doirq.c (renamed from nuttx/arch/arm/src/cortexm3/up_doirq.c)2
-rwxr-xr-xnuttx/arch/arm/src/armv7-m/up_fullcontextrestore.S (renamed from nuttx/arch/arm/src/cortexm3/up_fullcontextrestore.S)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_hardfault.c (renamed from nuttx/arch/arm/src/cortexm3/up_hardfault.c)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_initialstate.c (renamed from nuttx/arch/arm/src/cortexm3/up_initialstate.c)6
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_memfault.c (renamed from nuttx/arch/arm/src/cortexm3/up_memfault.c)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_mpu.c (renamed from nuttx/arch/arm/src/cortexm3/up_mpu.c)2
-rwxr-xr-xnuttx/arch/arm/src/armv7-m/up_releasepending.c (renamed from nuttx/arch/arm/src/cortexm3/up_releasepending.c)2
-rwxr-xr-xnuttx/arch/arm/src/armv7-m/up_reprioritizertr.c (renamed from nuttx/arch/arm/src/cortexm3/up_reprioritizertr.c)2
-rwxr-xr-xnuttx/arch/arm/src/armv7-m/up_saveusercontext.S (renamed from nuttx/arch/arm/src/cortexm3/up_saveusercontext.S)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c (renamed from nuttx/arch/arm/src/cortexm3/up_schedulesigaction.c)8
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_sigdeliver.c (renamed from nuttx/arch/arm/src/cortexm3/up_sigdeliver.c)2
-rw-r--r--nuttx/arch/arm/src/armv7-m/up_svcall.c (renamed from nuttx/arch/arm/src/cortexm3/up_svcall.c)2
-rwxr-xr-xnuttx/arch/arm/src/armv7-m/up_switchcontext.S (renamed from nuttx/arch/arm/src/cortexm3/up_switchcontext.S)2
-rwxr-xr-xnuttx/arch/arm/src/armv7-m/up_unblocktask.c (renamed from nuttx/arch/arm/src/cortexm3/up_unblocktask.c)2
-rw-r--r--nuttx/arch/arm/src/common/up_internal.h10
-rwxr-xr-xnuttx/arch/arm/src/kinetis/kinetis_memorymap.h4
-rw-r--r--nuttx/arch/arm/src/lm3s/lm3s_irq.c4
-rwxr-xr-xnuttx/arch/arm/src/lpc17xx/lpc17_irq.c4
-rwxr-xr-xnuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h2
-rwxr-xr-xnuttx/arch/arm/src/sam3u/sam3u_irq.c4
-rw-r--r--nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h2
-rw-r--r--nuttx/arch/arm/src/stm32/stm32_irq.c4
35 files changed, 317 insertions, 313 deletions
diff --git a/nuttx/arch/arm/include/cortexm3/irq.h b/nuttx/arch/arm/include/armv7-m/irq.h
index ff7134e5b..5b05c1d68 100644
--- a/nuttx/arch/arm/include/cortexm3/irq.h
+++ b/nuttx/arch/arm/include/armv7-m/irq.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/include/cortexm3/irq.h
+ * arch/arm/include/armv7-m/irq.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -37,8 +37,8 @@
* through nuttx/irq.h
*/
-#ifndef __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H
-#define __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
+#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
/****************************************************************************
* Included Files
@@ -312,5 +312,5 @@ extern "C" {
#endif
#endif
-#endif /* __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H */
diff --git a/nuttx/arch/arm/include/cortexm3/syscall.h b/nuttx/arch/arm/include/armv7-m/syscall.h
index bf61d7ee8..4c7b84302 100644
--- a/nuttx/arch/arm/include/cortexm3/syscall.h
+++ b/nuttx/arch/arm/include/armv7-m/syscall.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/include/cortexm3/syscall.h
+ * arch/arm/include/armv7-m/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -37,8 +37,8 @@
* through include/syscall.h or include/sys/sycall.h
*/
-#ifndef __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H
-#define __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H
+#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
+#define __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
/****************************************************************************
* Included Files
@@ -239,5 +239,5 @@ extern "C" {
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H */
+#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H */
diff --git a/nuttx/arch/arm/include/irq.h b/nuttx/arch/arm/include/irq.h
index da8c09d36..71493a9fe 100644
--- a/nuttx/arch/arm/include/irq.h
+++ b/nuttx/arch/arm/include/irq.h
@@ -53,11 +53,11 @@
#include <arch/chip/irq.h>
/* Include ARM architecture-specific IRQ definitions (including register
- * save structure and irqsave()/irqrestore() macros
+ * save structure and irqsave()/irqrestore() macros)
*/
-#ifdef CONFIG_ARCH_CORTEXM3
-# include <arch/cortexm3/irq.h>
+#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
+# include <arch/armv7-m/irq.h>
#else
# include <arch/arm/irq.h>
#endif
diff --git a/nuttx/arch/arm/include/syscall.h b/nuttx/arch/arm/include/syscall.h
index 49a804d12..4c9eee63e 100644
--- a/nuttx/arch/arm/include/syscall.h
+++ b/nuttx/arch/arm/include/syscall.h
@@ -46,8 +46,8 @@
/* Include ARM architecture-specific syscall macros */
-#ifdef CONFIG_ARCH_CORTEXM3
-# include <arch/cortexm3/syscall.h>
+#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
+# include <arch/armv7-m/syscall.h>
#else
# include <arch/arm/syscall.h>
#endif
diff --git a/nuttx/arch/arm/src/Makefile b/nuttx/arch/arm/src/Makefile
index 0875ad95c..093ec0433 100644
--- a/nuttx/arch/arm/src/Makefile
+++ b/nuttx/arch/arm/src/Makefile
@@ -37,11 +37,15 @@
-include chip/Make.defs
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
-ifeq ($(CONFIG_ARCH_CORTEXM3),y)
-ARCH_SUBDIR = cortexm3
+ifeq ($(CONFIG_ARCH_CORTEXM3),y) /* Cortex-M3 is ARMv7-M */
+ARCH_SUBDIR = armv7-m
+else
+ifeq ($(CONFIG_ARCH_CORTEXM4),y) /* Cortex-M4 is ARMv7E-M */
+ARCH_SUBDIR = armv7-m
else
ARCH_SUBDIR = arm
endif
+endif
ifeq ($(WINTOOL),y)
NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx}"
diff --git a/nuttx/arch/arm/src/cortexm3/exc_return.h b/nuttx/arch/arm/src/armv7-m/exc_return.h
index 06c0e723f..f32fd7a06 100644
--- a/nuttx/arch/arm/src/cortexm3/exc_return.h
+++ b/nuttx/arch/arm/src/armv7-m/exc_return.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/cortexm3/exc_return.h
+ * arch/arm/src/armv7-m/exc_return.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/mpu.h b/nuttx/arch/arm/src/armv7-m/mpu.h
index 30d1d4af9..43746b507 100644
--- a/nuttx/arch/arm/src/cortexm3/mpu.h
+++ b/nuttx/arch/arm/src/armv7-m/mpu.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/cortexm3/mpu.h
+ * arch/arm/src/armv7-m/mpu.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/nvic.h b/nuttx/arch/arm/src/armv7-m/nvic.h
index c94a88a0e..b132b9966 100644
--- a/nuttx/arch/arm/src/cortexm3/nvic.h
+++ b/nuttx/arch/arm/src/armv7-m/nvic.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/cortexm3/nvic.h
+ * arch/arm/src/armv7-m/nvic.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H
-#define __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H
+#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H
+#define __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H
/************************************************************************************
* Included Files
@@ -48,7 +48,7 @@
/* NVIC base address ****************************************************************/
-#define CORTEXM3_NVIC_BASE 0xe000e000
+#define ARMV7M_NVIC_BASE 0xe000e000
/* NVIC register offsets ************************************************************/
@@ -216,166 +216,166 @@
/* NVIC register addresses **********************************************************/
-#define NVIC_INTCTRL_TYPE (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_TYPE_OFFSET)
-#define NVIC_SYSTICK_CTRL (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CTRL_OFFSET)
-#define NVIC_SYSTICK_RELOAD (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_RELOAD_OFFSET)
-#define NVIC_SYSTICK_CURRENT (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CURRENT_OFFSET)
-#define NVIC_SYSTICK_CALIB (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CALIB_OFFSET)
-
-#define NVIC_IRQ_ENABLE(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_ENABLE_OFFSET(n))
-#define NVIC_IRQ0_31_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_ENABLE_OFFSET)
-#define NVIC_IRQ32_63_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_ENABLE_OFFSET)
-#define NVIC_IRQ64_95_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_ENABLE_OFFSET)
-#define NVIC_IRQ96_127_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_ENABLE_OFFSET)
-#define NVIC_IRQ128_159_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_ENABLE_OFFSET)
-#define NVIC_IRQ160_191_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_ENABLE_OFFSET)
-#define NVIC_IRQ192_223_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_ENABLE_OFFSET)
-#define NVIC_IRQ224_239_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ENABLE_OFFSET)
-
-#define NVIC_IRQ_CLEAR(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_CLEAR_OFFSET(n))
-#define NVIC_IRQ0_31_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_CLEAR_OFFSET)
-#define NVIC_IRQ32_63_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_CLEAR_OFFSET)
-#define NVIC_IRQ64_95_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_CLEAR_OFFSET)
-#define NVIC_IRQ96_127_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_CLEAR_OFFSET)
-#define NVIC_IRQ128_159_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_CLEAR_OFFSET)
-#define NVIC_IRQ160_191_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_CLEAR_OFFSET)
-#define NVIC_IRQ192_223_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_CLEAR_OFFSET)
-#define NVIC_IRQ224_239_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_CLEAR_OFFSET)
-
-#define NVIC_IRQ_PEND(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_PEND_OFFSET(n))
-#define NVIC_IRQ0_31_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_PEND_OFFSET)
-#define NVIC_IRQ32_63_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_PEND_OFFSET)
-#define NVIC_IRQ64_95_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_PEND_OFFSET)
-#define NVIC_IRQ96_127_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_PEND_OFFSET)
-#define NVIC_IRQ128_159_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_PEND_OFFSET)
-#define NVIC_IRQ160_191_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_PEND_OFFSET)
-#define NVIC_IRQ192_223_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_PEND_OFFSET)
-#define NVIC_IRQ224_239_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_PEND_OFFSET)
-
-#define NVIC_IRQ_CLRPEND(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_CLRPEND_OFFSET(n))
-#define NVIC_IRQ0_31_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_CLRPEND_OFFSET)
-#define NVIC_IRQ32_63_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_CLRPEND_OFFSET)
-#define NVIC_IRQ64_95_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_CLRPEND_OFFSET)
-#define NVIC_IRQ96_127_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_CLRPEND_OFFSET)
-#define NVIC_IRQ128_159_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_CLRPEND_OFFSET)
-#define NVIC_IRQ160_191_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_CLRPEND_OFFSET)
-#define NVIC_IRQ192_223_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_CLRPEND_OFFSET)
-#define NVIC_IRQ224_239_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_CLRPEND_OFFSET)
-
-#define NVIC_IRQ_ACTIVE(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_ACTIVE_OFFSET(n))
-#define NVIC_IRQ0_31_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_ACTIVE_OFFSET)
-#define NVIC_IRQ32_63_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_ACTIVE_OFFSET)
-#define NVIC_IRQ64_95_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_ACTIVE_OFFSET)
-#define NVIC_IRQ96_127_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_ACTIVE_OFFSET)
-#define NVIC_IRQ128_159_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_ACTIVE_OFFSET)
-#define NVIC_IRQ160_191_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_ACTIVE_OFFSET)
-#define NVIC_IRQ192_223_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_ACTIVE_OFFSET)
-#define NVIC_IRQ224_239_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ACTIVE_OFFSET)
-
-#define NVIC_IRQ_PRIORITY(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_PRIORITY_OFFSET(n))
-#define NVIC_IRQ0_3_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ0_3_PRIORITY_OFFSET)
-#define NVIC_IRQ4_7_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ4_7_PRIORITY_OFFSET)
-#define NVIC_IRQ8_11_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ8_11_PRIORITY_OFFSET)
-#define NVIC_IRQ12_15_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ12_15_PRIORITY_OFFSET)
-#define NVIC_IRQ16_19_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ16_19_PRIORITY_OFFSET)
-#define NVIC_IRQ20_23_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ20_23_PRIORITY_OFFSET)
-#define NVIC_IRQ24_27_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ24_27_PRIORITY_OFFSET)
-#define NVIC_IRQ28_31_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ28_31_PRIORITY_OFFSET)
-#define NVIC_IRQ32_35_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ32_35_PRIORITY_OFFSET)
-#define NVIC_IRQ36_39_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ36_39_PRIORITY_OFFSET)
-#define NVIC_IRQ40_43_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ40_43_PRIORITY_OFFSET)
-#define NVIC_IRQ44_47_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ44_47_PRIORITY_OFFSET)
-#define NVIC_IRQ48_51_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ48_51_PRIORITY_OFFSET)
-#define NVIC_IRQ52_55_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ52_55_PRIORITY_OFFSET)
-#define NVIC_IRQ56_59_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ56_59_PRIORITY_OFFSET)
-#define NVIC_IRQ60_63_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ60_63_PRIORITY_OFFSET)
-#define NVIC_IRQ64_67_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ64_67_PRIORITY_OFFSET)
-#define NVIC_IRQ68_71_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ68_71_PRIORITY_OFFSET)
-#define NVIC_IRQ72_75_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ72_75_PRIORITY_OFFSET)
-#define NVIC_IRQ76_79_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ76_79_PRIORITY_OFFSET)
-#define NVIC_IRQ80_83_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ80_83_PRIORITY_OFFSET)
-#define NVIC_IRQ84_87_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ84_87_PRIORITY_OFFSET)
-#define NVIC_IRQ88_91_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ88_91_PRIORITY_OFFSET)
-#define NVIC_IRQ92_95_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ92_95_PRIORITY_OFFSET)
-#define NVIC_IRQ96_99_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ96_99_PRIORITY_OFFSET)
-#define NVIC_IRQ100_103_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ100_103_PRIORITY_OFFSET)
-#define NVIC_IRQ104_107_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ104_107_PRIORITY_OFFSET)
-#define NVIC_IRQ108_111_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ108_111_PRIORITY_OFFSET)
-#define NVIC_IRQ112_115_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ112_115_PRIORITY_OFFSET)
-#define NVIC_IRQ116_119_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ116_119_PRIORITY_OFFSET)
-#define NVIC_IRQ120_123_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ120_123_PRIORITY_OFFSET)
-#define NVIC_IRQ124_127_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ124_127_PRIORITY_OFFSET)
-#define NVIC_IRQ128_131_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ128_131_PRIORITY_OFFSET)
-#define NVIC_IRQ132_135_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ132_135_PRIORITY_OFFSET)
-#define NVIC_IRQ136_139_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ136_139_PRIORITY_OFFSET)
-#define NVIC_IRQ140_143_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ140_143_PRIORITY_OFFSET)
-#define NVIC_IRQ144_147_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ144_147_PRIORITY_OFFSET)
-#define NVIC_IRQ148_151_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ148_151_PRIORITY_OFFSET)
-#define NVIC_IRQ152_155_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ152_155_PRIORITY_OFFSET)
-#define NVIC_IRQ156_159_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ156_159_PRIORITY_OFFSET)
-#define NVIC_IRQ160_163_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ160_163_PRIORITY_OFFSET)
-#define NVIC_IRQ164_167_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ164_167_PRIORITY_OFFSET)
-#define NVIC_IRQ168_171_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ168_171_PRIORITY_OFFSET)
-#define NVIC_IRQ172_175_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ172_175_PRIORITY_OFFSET)
-#define NVIC_IRQ176_179_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ176_179_PRIORITY_OFFSET)
-#define NVIC_IRQ180_183_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ180_183_PRIORITY_OFFSET)
-#define NVIC_IRQ184_187_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ184_187_PRIORITY_OFFSET)
-#define NVIC_IRQ188_191_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ188_191_PRIORITY_OFFSET)
-#define NVIC_IRQ192_195_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ192_195_PRIORITY_OFFSET)
-#define NVIC_IRQ196_199_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ196_199_PRIORITY_OFFSET)
-#define NVIC_IRQ200_203_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ200_203_PRIORITY_OFFSET)
-#define NVIC_IRQ204_207_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ204_207_PRIORITY_OFFSET)
-#define NVIC_IRQ208_211_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ208_211_PRIORITY_OFFSET)
-#define NVIC_IRQ212_215_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ212_215_PRIORITY_OFFSET)
-#define NVIC_IRQ216_219_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ216_219_PRIORITY_OFFSET)
-#define NVIC_IRQ220_223_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ220_223_PRIORITY_OFFSET)
-#define NVIC_IRQ224_227_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ224_227_PRIORITY_OFFSET)
-#define NVIC_IRQ228_231_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ228_231_PRIORITY_OFFSET)
-#define NVIC_IRQ232_235_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ232_235_PRIORITY_OFFSET)
-
-#define NVIC_CPUID_BASE (CORTEXM3_NVIC_BASE + NVIC_CPUID_BASE_OFFSET)
-#define NVIC_INTCTRL (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_OFFSET)
-#define NVIC_VECTAB (CORTEXM3_NVIC_BASE + NVIC_VECTAB_OFFSET)
-#define NVIC_AIRC (CORTEXM3_NVIC_BASE + NVIC_AIRC_OFFSET)
-#define NVIC_SYSCON (CORTEXM3_NVIC_BASE + NVIC_SYSCON_OFFSET)
-#define NVIC_CFGCON (CORTEXM3_NVIC_BASE + NVIC_CFGCON_OFFSET)
-#define NVIC_SYSH_PRIORITY(n) (CORTEXM3_NVIC_BASE + NVIC_SYSH_PRIORITY_OFFSET(n))
-#define NVIC_SYSH4_7_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_SYSH4_7_PRIORITY_OFFSET)
-#define NVIC_SYSH8_11_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_SYSH8_11_PRIORITY_OFFSET)
-#define NVIC_SYSH12_15_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_SYSH12_15_PRIORITY_OFFSET)
-#define NVIC_SYSHCON (CORTEXM3_NVIC_BASE + NVIC_SYSHCON_OFFSET)
-#define NVIC_CFAULTS (CORTEXM3_NVIC_BASE + NVIC_CFAULTS_OFFSET)
-#define NVIC_HFAULTS (CORTEXM3_NVIC_BASE + NVIC_HFAULTS_OFFSET)
-#define NVIC_DFAULTS (CORTEXM3_NVIC_BASE + NVIC_DFAULTS_OFFSET)
-#define NVIC_MEMMANAGE_ADDR (CORTEXM3_NVIC_BASE + NVIC_MEMMANAGE_ADDR_OFFSET)
-#define NVIC_BFAULT_ADDR (CORTEXM3_NVIC_BASE + NVIC_BFAULT_ADDR_OFFSET)
-#define NVIC_AFAULTS (CORTEXM3_NVIC_BASE + NVIC_AFAULTS_OFFSET)
-#define NVIC_PFR0 (CORTEXM3_NVIC_BASE + NVIC_PFR0_OFFSET)
-#define NVIC_PFR1 (CORTEXM3_NVIC_BASE + NVIC_PFR1_OFFSET)
-#define NVIC_DFR0 (CORTEXM3_NVIC_BASE + NVIC_DFR0_OFFSET)
-#define NVIC_AFR0 (CORTEXM3_NVIC_BASE + NVIC_AFR0_OFFSET)
-#define NVIC_MMFR0 (CORTEXM3_NVIC_BASE + NVIC_MMFR0_OFFSET)
-#define NVIC_MMFR1 (CORTEXM3_NVIC_BASE + NVIC_MMFR1_OFFSET)
-#define NVIC_MMFR2 (CORTEXM3_NVIC_BASE + NVIC_MMFR2_OFFSET)
-#define NVIC_MMFR3 (CORTEXM3_NVIC_BASE + NVIC_MMFR3_OFFSET)
-#define NVIC_ISAR0 (CORTEXM3_NVIC_BASE + NVIC_ISAR0_OFFSET)
-#define NVIC_ISAR1 (CORTEXM3_NVIC_BASE + NVIC_ISAR1_OFFSET)
-#define NVIC_ISAR2 (CORTEXM3_NVIC_BASE + NVIC_ISAR2_OFFSET)
-#define NVIC_ISAR3 (CORTEXM3_NVIC_BASE + NVIC_ISAR3_OFFSET)
-#define NVIC_ISAR4 (CORTEXM3_NVIC_BASE + NVIC_ISAR4_OFFSET)
-#define NVIC_STIR (CORTEXM3_NVIC_BASE + NVIC_STIR_OFFSET)
-#define NVIC_PID4 (CORTEXM3_NVIC_BASE + NVIC_PID4_OFFSET)
-#define NVIC_PID5 (CORTEXM3_NVIC_BASE + NVIC_PID5_OFFSET)
-#define NVIC_PID6 (CORTEXM3_NVIC_BASE + NVIC_PID6_OFFSET)
-#define NVIC_PID7 (CORTEXM3_NVIC_BASE + NVIC_PID7_OFFSET)
-#define NVIC_PID0 (CORTEXM3_NVIC_BASE + NVIC_PID0_OFFSET)
-#define NVIC_PID1 (CORTEXM3_NVIC_BASE + NVIC_PID1_OFFSET)
-#define NVIC_PID2 (CORTEXM3_NVIC_BASE + NVIC_PID2_OFFSET)
-#define NVIC_PID3 (CORTEXM3_NVIC_BASE + NVIC_PID3_OFFSET)
-#define NVIC_CID0 (CORTEXM3_NVIC_BASE + NVIC_CID0_OFFSET)
-#define NVIC_CID1 (CORTEXM3_NVIC_BASE + NVIC_CID1_OFFSET)
-#define NVIC_CID2 (CORTEXM3_NVIC_BASE + NVIC_CID2_OFFSET)
-#define NVIC_CID3 (CORTEXM3_NVIC_BASE + NVIC_CID3_OFFSET)
+#define NVIC_INTCTRL_TYPE (ARMV7M_NVIC_BASE + NVIC_INTCTRL_TYPE_OFFSET)
+#define NVIC_SYSTICK_CTRL (ARMV7M_NVIC_BASE + NVIC_SYSTICK_CTRL_OFFSET)
+#define NVIC_SYSTICK_RELOAD (ARMV7M_NVIC_BASE + NVIC_SYSTICK_RELOAD_OFFSET)
+#define NVIC_SYSTICK_CURRENT (ARMV7M_NVIC_BASE + NVIC_SYSTICK_CURRENT_OFFSET)
+#define NVIC_SYSTICK_CALIB (ARMV7M_NVIC_BASE + NVIC_SYSTICK_CALIB_OFFSET)
+
+#define NVIC_IRQ_ENABLE(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_ENABLE_OFFSET(n))
+#define NVIC_IRQ0_31_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_ENABLE_OFFSET)
+#define NVIC_IRQ32_63_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_ENABLE_OFFSET)
+#define NVIC_IRQ64_95_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_ENABLE_OFFSET)
+#define NVIC_IRQ96_127_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_ENABLE_OFFSET)
+#define NVIC_IRQ128_159_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_ENABLE_OFFSET)
+#define NVIC_IRQ160_191_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_ENABLE_OFFSET)
+#define NVIC_IRQ192_223_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_ENABLE_OFFSET)
+#define NVIC_IRQ224_239_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_ENABLE_OFFSET)
+
+#define NVIC_IRQ_CLEAR(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_CLEAR_OFFSET(n))
+#define NVIC_IRQ0_31_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_CLEAR_OFFSET)
+#define NVIC_IRQ32_63_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_CLEAR_OFFSET)
+#define NVIC_IRQ64_95_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_CLEAR_OFFSET)
+#define NVIC_IRQ96_127_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_CLEAR_OFFSET)
+#define NVIC_IRQ128_159_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_CLEAR_OFFSET)
+#define NVIC_IRQ160_191_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_CLEAR_OFFSET)
+#define NVIC_IRQ192_223_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_CLEAR_OFFSET)
+#define NVIC_IRQ224_239_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_CLEAR_OFFSET)
+
+#define NVIC_IRQ_PEND(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_PEND_OFFSET(n))
+#define NVIC_IRQ0_31_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_PEND_OFFSET)
+#define NVIC_IRQ32_63_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_PEND_OFFSET)
+#define NVIC_IRQ64_95_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_PEND_OFFSET)
+#define NVIC_IRQ96_127_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_PEND_OFFSET)
+#define NVIC_IRQ128_159_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_PEND_OFFSET)
+#define NVIC_IRQ160_191_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_PEND_OFFSET)
+#define NVIC_IRQ192_223_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_PEND_OFFSET)
+#define NVIC_IRQ224_239_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_PEND_OFFSET)
+
+#define NVIC_IRQ_CLRPEND(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_CLRPEND_OFFSET(n))
+#define NVIC_IRQ0_31_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_CLRPEND_OFFSET)
+#define NVIC_IRQ32_63_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_CLRPEND_OFFSET)
+#define NVIC_IRQ64_95_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_CLRPEND_OFFSET)
+#define NVIC_IRQ96_127_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_CLRPEND_OFFSET)
+#define NVIC_IRQ128_159_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_CLRPEND_OFFSET)
+#define NVIC_IRQ160_191_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_CLRPEND_OFFSET)
+#define NVIC_IRQ192_223_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_CLRPEND_OFFSET)
+#define NVIC_IRQ224_239_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_CLRPEND_OFFSET)
+
+#define NVIC_IRQ_ACTIVE(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_ACTIVE_OFFSET(n))
+#define NVIC_IRQ0_31_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_ACTIVE_OFFSET)
+#define NVIC_IRQ32_63_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_ACTIVE_OFFSET)
+#define NVIC_IRQ64_95_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_ACTIVE_OFFSET)
+#define NVIC_IRQ96_127_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_ACTIVE_OFFSET)
+#define NVIC_IRQ128_159_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_ACTIVE_OFFSET)
+#define NVIC_IRQ160_191_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_ACTIVE_OFFSET)
+#define NVIC_IRQ192_223_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_ACTIVE_OFFSET)
+#define NVIC_IRQ224_239_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_ACTIVE_OFFSET)
+
+#define NVIC_IRQ_PRIORITY(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_PRIORITY_OFFSET(n))
+#define NVIC_IRQ0_3_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ0_3_PRIORITY_OFFSET)
+#define NVIC_IRQ4_7_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ4_7_PRIORITY_OFFSET)
+#define NVIC_IRQ8_11_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ8_11_PRIORITY_OFFSET)
+#define NVIC_IRQ12_15_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ12_15_PRIORITY_OFFSET)
+#define NVIC_IRQ16_19_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ16_19_PRIORITY_OFFSET)
+#define NVIC_IRQ20_23_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ20_23_PRIORITY_OFFSET)
+#define NVIC_IRQ24_27_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ24_27_PRIORITY_OFFSET)
+#define NVIC_IRQ28_31_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ28_31_PRIORITY_OFFSET)
+#define NVIC_IRQ32_35_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ32_35_PRIORITY_OFFSET)
+#define NVIC_IRQ36_39_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ36_39_PRIORITY_OFFSET)
+#define NVIC_IRQ40_43_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ40_43_PRIORITY_OFFSET)
+#define NVIC_IRQ44_47_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ44_47_PRIORITY_OFFSET)
+#define NVIC_IRQ48_51_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ48_51_PRIORITY_OFFSET)
+#define NVIC_IRQ52_55_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ52_55_PRIORITY_OFFSET)
+#define NVIC_IRQ56_59_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ56_59_PRIORITY_OFFSET)
+#define NVIC_IRQ60_63_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ60_63_PRIORITY_OFFSET)
+#define NVIC_IRQ64_67_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ64_67_PRIORITY_OFFSET)
+#define NVIC_IRQ68_71_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ68_71_PRIORITY_OFFSET)
+#define NVIC_IRQ72_75_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ72_75_PRIORITY_OFFSET)
+#define NVIC_IRQ76_79_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ76_79_PRIORITY_OFFSET)
+#define NVIC_IRQ80_83_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ80_83_PRIORITY_OFFSET)
+#define NVIC_IRQ84_87_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ84_87_PRIORITY_OFFSET)
+#define NVIC_IRQ88_91_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ88_91_PRIORITY_OFFSET)
+#define NVIC_IRQ92_95_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ92_95_PRIORITY_OFFSET)
+#define NVIC_IRQ96_99_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ96_99_PRIORITY_OFFSET)
+#define NVIC_IRQ100_103_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ100_103_PRIORITY_OFFSET)
+#define NVIC_IRQ104_107_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ104_107_PRIORITY_OFFSET)
+#define NVIC_IRQ108_111_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ108_111_PRIORITY_OFFSET)
+#define NVIC_IRQ112_115_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ112_115_PRIORITY_OFFSET)
+#define NVIC_IRQ116_119_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ116_119_PRIORITY_OFFSET)
+#define NVIC_IRQ120_123_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ120_123_PRIORITY_OFFSET)
+#define NVIC_IRQ124_127_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ124_127_PRIORITY_OFFSET)
+#define NVIC_IRQ128_131_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ128_131_PRIORITY_OFFSET)
+#define NVIC_IRQ132_135_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ132_135_PRIORITY_OFFSET)
+#define NVIC_IRQ136_139_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ136_139_PRIORITY_OFFSET)
+#define NVIC_IRQ140_143_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ140_143_PRIORITY_OFFSET)
+#define NVIC_IRQ144_147_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ144_147_PRIORITY_OFFSET)
+#define NVIC_IRQ148_151_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ148_151_PRIORITY_OFFSET)
+#define NVIC_IRQ152_155_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ152_155_PRIORITY_OFFSET)
+#define NVIC_IRQ156_159_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ156_159_PRIORITY_OFFSET)
+#define NVIC_IRQ160_163_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ160_163_PRIORITY_OFFSET)
+#define NVIC_IRQ164_167_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ164_167_PRIORITY_OFFSET)
+#define NVIC_IRQ168_171_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ168_171_PRIORITY_OFFSET)
+#define NVIC_IRQ172_175_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ172_175_PRIORITY_OFFSET)
+#define NVIC_IRQ176_179_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ176_179_PRIORITY_OFFSET)
+#define NVIC_IRQ180_183_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ180_183_PRIORITY_OFFSET)
+#define NVIC_IRQ184_187_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ184_187_PRIORITY_OFFSET)
+#define NVIC_IRQ188_191_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ188_191_PRIORITY_OFFSET)
+#define NVIC_IRQ192_195_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ192_195_PRIORITY_OFFSET)
+#define NVIC_IRQ196_199_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ196_199_PRIORITY_OFFSET)
+#define NVIC_IRQ200_203_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ200_203_PRIORITY_OFFSET)
+#define NVIC_IRQ204_207_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ204_207_PRIORITY_OFFSET)
+#define NVIC_IRQ208_211_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ208_211_PRIORITY_OFFSET)
+#define NVIC_IRQ212_215_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ212_215_PRIORITY_OFFSET)
+#define NVIC_IRQ216_219_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ216_219_PRIORITY_OFFSET)
+#define NVIC_IRQ220_223_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ220_223_PRIORITY_OFFSET)
+#define NVIC_IRQ224_227_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ224_227_PRIORITY_OFFSET)
+#define NVIC_IRQ228_231_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ228_231_PRIORITY_OFFSET)
+#define NVIC_IRQ232_235_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ232_235_PRIORITY_OFFSET)
+
+#define NVIC_CPUID_BASE (ARMV7M_NVIC_BASE + NVIC_CPUID_BASE_OFFSET)
+#define NVIC_INTCTRL (ARMV7M_NVIC_BASE + NVIC_INTCTRL_OFFSET)
+#define NVIC_VECTAB (ARMV7M_NVIC_BASE + NVIC_VECTAB_OFFSET)
+#define NVIC_AIRC (ARMV7M_NVIC_BASE + NVIC_AIRC_OFFSET)
+#define NVIC_SYSCON (ARMV7M_NVIC_BASE + NVIC_SYSCON_OFFSET)
+#define NVIC_CFGCON (ARMV7M_NVIC_BASE + NVIC_CFGCON_OFFSET)
+#define NVIC_SYSH_PRIORITY(n) (ARMV7M_NVIC_BASE + NVIC_SYSH_PRIORITY_OFFSET(n))
+#define NVIC_SYSH4_7_PRIORITY (ARMV7M_NVIC_BASE + NVIC_SYSH4_7_PRIORITY_OFFSET)
+#define NVIC_SYSH8_11_PRIORITY (ARMV7M_NVIC_BASE + NVIC_SYSH8_11_PRIORITY_OFFSET)
+#define NVIC_SYSH12_15_PRIORITY (ARMV7M_NVIC_BASE + NVIC_SYSH12_15_PRIORITY_OFFSET)
+#define NVIC_SYSHCON (ARMV7M_NVIC_BASE + NVIC_SYSHCON_OFFSET)
+#define NVIC_CFAULTS (ARMV7M_NVIC_BASE + NVIC_CFAULTS_OFFSET)
+#define NVIC_HFAULTS (ARMV7M_NVIC_BASE + NVIC_HFAULTS_OFFSET)
+#define NVIC_DFAULTS (ARMV7M_NVIC_BASE + NVIC_DFAULTS_OFFSET)
+#define NVIC_MEMMANAGE_ADDR (ARMV7M_NVIC_BASE + NVIC_MEMMANAGE_ADDR_OFFSET)
+#define NVIC_BFAULT_ADDR (ARMV7M_NVIC_BASE + NVIC_BFAULT_ADDR_OFFSET)
+#define NVIC_AFAULTS (ARMV7M_NVIC_BASE + NVIC_AFAULTS_OFFSET)
+#define NVIC_PFR0 (ARMV7M_NVIC_BASE + NVIC_PFR0_OFFSET)
+#define NVIC_PFR1 (ARMV7M_NVIC_BASE + NVIC_PFR1_OFFSET)
+#define NVIC_DFR0 (ARMV7M_NVIC_BASE + NVIC_DFR0_OFFSET)
+#define NVIC_AFR0 (ARMV7M_NVIC_BASE + NVIC_AFR0_OFFSET)
+#define NVIC_MMFR0 (ARMV7M_NVIC_BASE + NVIC_MMFR0_OFFSET)
+#define NVIC_MMFR1 (ARMV7M_NVIC_BASE + NVIC_MMFR1_OFFSET)
+#define NVIC_MMFR2 (ARMV7M_NVIC_BASE + NVIC_MMFR2_OFFSET)
+#define NVIC_MMFR3 (ARMV7M_NVIC_BASE + NVIC_MMFR3_OFFSET)
+#define NVIC_ISAR0 (ARMV7M_NVIC_BASE + NVIC_ISAR0_OFFSET)
+#define NVIC_ISAR1 (ARMV7M_NVIC_BASE + NVIC_ISAR1_OFFSET)
+#define NVIC_ISAR2 (ARMV7M_NVIC_BASE + NVIC_ISAR2_OFFSET)
+#define NVIC_ISAR3 (ARMV7M_NVIC_BASE + NVIC_ISAR3_OFFSET)
+#define NVIC_ISAR4 (ARMV7M_NVIC_BASE + NVIC_ISAR4_OFFSET)
+#define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
+#define NVIC_PID4 (ARMV7M_NVIC_BASE + NVIC_PID4_OFFSET)
+#define NVIC_PID5 (ARMV7M_NVIC_BASE + NVIC_PID5_OFFSET)
+#define NVIC_PID6 (ARMV7M_NVIC_BASE + NVIC_PID6_OFFSET)
+#define NVIC_PID7 (ARMV7M_NVIC_BASE + NVIC_PID7_OFFSET)
+#define NVIC_PID0 (ARMV7M_NVIC_BASE + NVIC_PID0_OFFSET)
+#define NVIC_PID1 (ARMV7M_NVIC_BASE + NVIC_PID1_OFFSET)
+#define NVIC_PID2 (ARMV7M_NVIC_BASE + NVIC_PID2_OFFSET)
+#define NVIC_PID3 (ARMV7M_NVIC_BASE + NVIC_PID3_OFFSET)
+#define NVIC_CID0 (ARMV7M_NVIC_BASE + NVIC_CID0_OFFSET)
+#define NVIC_CID1 (ARMV7M_NVIC_BASE + NVIC_CID1_OFFSET)
+#define NVIC_CID2 (ARMV7M_NVIC_BASE + NVIC_CID2_OFFSET)
+#define NVIC_CID3 (ARMV7M_NVIC_BASE + NVIC_CID3_OFFSET)
/* NVIC register bit definitions ****************************************************/
@@ -386,92 +386,92 @@
/* SysTick control and status register (SYSTICK_CTRL) */
-#define NVIC_SYSTICK_CTRL_ENABLE (1 << 0) /* Bit 0: Enable */
-#define NVIC_SYSTICK_CTRL_TICKINT (1 << 1) /* Bit 1: Tick interrupt */
-#define NVIC_SYSTICK_CTRL_CLKSOURCE (1 << 2) /* Bit 2: Clock source */
-#define NVIC_SYSTICK_CTRL_COUNTFLAG (1 << 16) /* Bit 16: Count Flag */
+#define NVIC_SYSTICK_CTRL_ENABLE (1 << 0) /* Bit 0: Enable */
+#define NVIC_SYSTICK_CTRL_TICKINT (1 << 1) /* Bit 1: Tick interrupt */
+#define NVIC_SYSTICK_CTRL_CLKSOURCE (1 << 2) /* Bit 2: Clock source */
+#define NVIC_SYSTICK_CTRL_COUNTFLAG (1 << 16) /* Bit 16: Count Flag */
/* SysTick reload value register (SYSTICK_RELOAD) */
-#define NVIC_SYSTICK_RELOAD_SHIFT 0 /* Bits 23-0: Timer reload value */
-#define NVIC_SYSTICK_RELOAD_MASK (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
+#define NVIC_SYSTICK_RELOAD_SHIFT 0 /* Bits 23-0: Timer reload value */
+#define NVIC_SYSTICK_RELOAD_MASK (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
/* SysTick current value registe (SYSTICK_CURRENT) */
-#define NVIC_SYSTICK_CURRENT_SHIFT 0 /* Bits 23-0: Timer current value */
-#define NVIC_SYSTICK_CURRENT_MASK (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
+#define NVIC_SYSTICK_CURRENT_SHIFT 0 /* Bits 23-0: Timer current value */
+#define NVIC_SYSTICK_CURRENT_MASK (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
/* SysTick calibration value register (SYSTICK_CALIB) */
-#define NVIC_SYSTICK_CALIB_TENMS_SHIFT 0 /* Bits 23-0: Calibration value */
-#define NVIC_SYSTICK_CALIB_TENMS_MASK (0x00ffffff << NVIC_SYSTICK_CALIB_TENMS_SHIFT)
-#define NVIC_SYSTICK_CALIB_SKEW (1 << 30) /* Bit 30: Calibration value inexact */
-#define NVIC_SYSTICK_CALIB_NOREF (1 << 31) /* Bit 31: No external reference clock */
+#define NVIC_SYSTICK_CALIB_TENMS_SHIFT 0 /* Bits 23-0: Calibration value */
+#define NVIC_SYSTICK_CALIB_TENMS_MASK (0x00ffffff << NVIC_SYSTICK_CALIB_TENMS_SHIFT)
+#define NVIC_SYSTICK_CALIB_SKEW (1 << 30) /* Bit 30: Calibration value inexact */
+#define NVIC_SYSTICK_CALIB_NOREF (1 << 31) /* Bit 31: No external reference clock */
/* Interrupt control state register (INTCTRL) */
-#define NVIC_INTCTRL_NMIPENDSET (1 << 31) /* Bit 31: Set pending NMI bit */
-#define NVIC_INTCTRL_PENDSVSET (1 << 28) /* Bit 28: Set pending PendSV bit */
-#define NVIC_INTCTRL_PENDSVCLR (1 << 27) /* Bit 27: Clear pending PendSV bit */
-#define NVIC_INTCTRL_PENDSTSET (1 << 26) /* Bit 26: Set pending SysTick bit */
-#define NVIC_INTCTRL_PENDSTCLR (1 << 25) /* Bit 25: Clear pending SysTick bit */
-#define NVIC_INTCTRL_ISPREEMPOT (1 << 23) /* Bit 23: Pending active next cycle */
-#define NVIC_INTCTRL_ISRPENDING (1 << 22) /* Bit 22: Interrupt pending flag */
-#define NVIC_INTCTRL_VECTPENDING_SHIFT 12 /* Bits 21-12: Pending ISR number field */
-#define NVIC_INTCTRL_VECTPENDING_MASK (0x3ff << NVIC_INTCTRL_VECTPENDING_SHIFT)
-#define NVIC_INTCTRL_RETTOBASE (1 << 11) /* Bit 11: no other exceptions pending */
-#define NVIC_INTCTRL_VECTACTIVE_SHIFT 0 /* Bits 8-0: Active ISR number */
-#define NVIC_INTCTRL_VECTACTIVE_MASK (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT)
+#define NVIC_INTCTRL_NMIPENDSET (1 << 31) /* Bit 31: Set pending NMI bit */
+#define NVIC_INTCTRL_PENDSVSET (1 << 28) /* Bit 28: Set pending PendSV bit */
+#define NVIC_INTCTRL_PENDSVCLR (1 << 27) /* Bit 27: Clear pending PendSV bit */
+#define NVIC_INTCTRL_PENDSTSET (1 << 26) /* Bit 26: Set pending SysTick bit */
+#define NVIC_INTCTRL_PENDSTCLR (1 << 25) /* Bit 25: Clear pending SysTick bit */
+#define NVIC_INTCTRL_ISPREEMPOT (1 << 23) /* Bit 23: Pending active next cycle */
+#define NVIC_INTCTRL_ISRPENDING (1 << 22) /* Bit 22: Interrupt pending flag */
+#define NVIC_INTCTRL_VECTPENDING_SHIFT 12 /* Bits 21-12: Pending ISR number field */
+#define NVIC_INTCTRL_VECTPENDING_MASK (0x3ff << NVIC_INTCTRL_VECTPENDING_SHIFT)
+#define NVIC_INTCTRL_RETTOBASE (1 << 11) /* Bit 11: no other exceptions pending */
+#define NVIC_INTCTRL_VECTACTIVE_SHIFT 0 /* Bits 8-0: Active ISR number */
+#define NVIC_INTCTRL_VECTACTIVE_MASK (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT)
/* System handler 4-7 priority register */
-#define NVIC_SYSH_PRIORITY_PR4_SHIFT 0
-#define NVIC_SYSH_PRIORITY_PR4_MASK (0xff << NVIC_SYSH_PRIORITY_PR4_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR5_SHIFT 8
-#define NVIC_SYSH_PRIORITY_PR5_MASK (0xff << NVIC_SYSH_PRIORITY_PR5_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR6_SHIFT 16
-#define NVIC_SYSH_PRIORITY_PR6_MASK (0xff << NVIC_SYSH_PRIORITY_PR6_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR7_SHIFT 24
-#define NVIC_SYSH_PRIORITY_PR7_MASK (0xff << NVIC_SYSH_PRIORITY_PR7_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR4_SHIFT 0
+#define NVIC_SYSH_PRIORITY_PR4_MASK (0xff << NVIC_SYSH_PRIORITY_PR4_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR5_SHIFT 8
+#define NVIC_SYSH_PRIORITY_PR5_MASK (0xff << NVIC_SYSH_PRIORITY_PR5_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR6_SHIFT 16
+#define NVIC_SYSH_PRIORITY_PR6_MASK (0xff << NVIC_SYSH_PRIORITY_PR6_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR7_SHIFT 24
+#define NVIC_SYSH_PRIORITY_PR7_MASK (0xff << NVIC_SYSH_PRIORITY_PR7_SHIFT)
/* System handler 8-11 priority register */
-#define NVIC_SYSH_PRIORITY_PR8_SHIFT 0
-#define NVIC_SYSH_PRIORITY_PR8_MASK (0xff << NVIC_SYSH_PRIORITY_PR8_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR9_SHIFT 8
-#define NVIC_SYSH_PRIORITY_PR9_MASK (0xff << NVIC_SYSH_PRIORITY_PR9_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR10_SHIFT 16
-#define NVIC_SYSH_PRIORITY_PR10_MASK (0xff << NVIC_SYSH_PRIORITY_PR10_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR11_SHIFT 24
-#define NVIC_SYSH_PRIORITY_PR11_MASK (0xff << NVIC_SYSH_PRIORITY_PR11_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR8_SHIFT 0
+#define NVIC_SYSH_PRIORITY_PR8_MASK (0xff << NVIC_SYSH_PRIORITY_PR8_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR9_SHIFT 8
+#define NVIC_SYSH_PRIORITY_PR9_MASK (0xff << NVIC_SYSH_PRIORITY_PR9_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR10_SHIFT 16
+#define NVIC_SYSH_PRIORITY_PR10_MASK (0xff << NVIC_SYSH_PRIORITY_PR10_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR11_SHIFT 24
+#define NVIC_SYSH_PRIORITY_PR11_MASK (0xff << NVIC_SYSH_PRIORITY_PR11_SHIFT)
/* System handler 12-15 priority register */
-#define NVIC_SYSH_PRIORITY_PR12_SHIFT 0
-#define NVIC_SYSH_PRIORITY_PR12_MASK (0xff << NVIC_SYSH_PRIORITY_PR12_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR13_SHIFT 8
-#define NVIC_SYSH_PRIORITY_PR13_MASK (0xff << NVIC_SYSH_PRIORITY_PR13_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR14_SHIFT 16
-#define NVIC_SYSH_PRIORITY_PR14_MASK (0xff << NVIC_SYSH_PRIORITY_PR14_SHIFT)
-#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
-#define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR12_SHIFT 0
+#define NVIC_SYSH_PRIORITY_PR12_MASK (0xff << NVIC_SYSH_PRIORITY_PR12_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR13_SHIFT 8
+#define NVIC_SYSH_PRIORITY_PR13_MASK (0xff << NVIC_SYSH_PRIORITY_PR13_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR14_SHIFT 16
+#define NVIC_SYSH_PRIORITY_PR14_MASK (0xff << NVIC_SYSH_PRIORITY_PR14_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
+#define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
/* System handler control and state register (SYSHCON) */
-#define NVIC_SYSHCON_MEMFAULTACT (1 << 0) /* Bit 0: MemManage is active */
-#define NVIC_SYSHCON_BUSFAULTACT (1 << 1) /* Bit 1: BusFault is active */
-#define NVIC_SYSHCON_USGFAULTACT (1 << 3) /* Bit 3: UsageFault is active */
-#define NVIC_SYSHCON_SVCALLACT (1 << 7) /* Bit 7: SVCall is active */
-#define NVIC_SYSHCON_MONITORACT (1 << 8) /* Bit 8: Monitor is active */
-#define NVIC_SYSHCON_PENDSVACT (1 << 10) /* Bit 10: PendSV is active */
-#define NVIC_SYSHCON_SYSTICKACT (1 << 11) /* Bit 11: SysTick is active */
-#define NVIC_SYSHCON_USGFAULTPENDED (1 << 12) /* Bit 12: Usage fault is pended */
-#define NVIC_SYSHCON_MEMFAULTPENDED (1 << 13) /* Bit 13: MemManage is pended */
-#define NVIC_SYSHCON_BUSFAULTPENDED (1 << 14) /* Bit 14: BusFault is pended */
-#define NVIC_SYSHCON_SVCALLPENDED (1 << 15) /* Bit 15: SVCall is pended */
-#define NVIC_SYSHCON_MEMFAULTENA (1 << 16) /* Bit 16: MemFault enabled */
-#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
-#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
+#define NVIC_SYSHCON_MEMFAULTACT (1 << 0) /* Bit 0: MemManage is active */
+#define NVIC_SYSHCON_BUSFAULTACT (1 << 1) /* Bit 1: BusFault is active */
+#define NVIC_SYSHCON_USGFAULTACT (1 << 3) /* Bit 3: UsageFault is active */
+#define NVIC_SYSHCON_SVCALLACT (1 << 7) /* Bit 7: SVCall is active */
+#define NVIC_SYSHCON_MONITORACT (1 << 8) /* Bit 8: Monitor is active */
+#define NVIC_SYSHCON_PENDSVACT (1 << 10) /* Bit 10: PendSV is active */
+#define NVIC_SYSHCON_SYSTICKACT (1 << 11) /* Bit 11: SysTick is active */
+#define NVIC_SYSHCON_USGFAULTPENDED (1 << 12) /* Bit 12: Usage fault is pended */
+#define NVIC_SYSHCON_MEMFAULTPENDED (1 << 13) /* Bit 13: MemManage is pended */
+#define NVIC_SYSHCON_BUSFAULTPENDED (1 << 14) /* Bit 14: BusFault is pended */
+#define NVIC_SYSHCON_SVCALLPENDED (1 << 15) /* Bit 15: SVCall is pended */
+#define NVIC_SYSHCON_MEMFAULTENA (1 << 16) /* Bit 16: MemFault enabled */
+#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
+#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
/************************************************************************************
* Public Types
@@ -485,4 +485,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H */
+#endif /* __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H */
diff --git a/nuttx/arch/arm/src/cortexm3/psr.h b/nuttx/arch/arm/src/armv7-m/psr.h
index b392cfa3f..30913f7c9 100644
--- a/nuttx/arch/arm/src/cortexm3/psr.h
+++ b/nuttx/arch/arm/src/armv7-m/psr.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/cortexm3/psr.h
+ * arch/arm/src/armv7-m/psr.h
*
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H
-#define __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H
+#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H
+#define __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H
/************************************************************************************
* Included Files
@@ -46,42 +46,42 @@
/* Application Program Status Register (APSR) */
-#define CORTEXM3_APSR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
-#define CORTEXM3_APSR_V (1 << 28) /* Bit 28: Overflow flag */
-#define CORTEXM3_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */
-#define CORTEXM3_APSR_Z (1 << 30) /* Bit 30: Zero flag */
-#define CORTEXM3_APSR_N (1 << 31) /* Bit 31: Negative, less than flag */
+#define ARMV7M_APSR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
+#define ARMV7M_APSR_V (1 << 28) /* Bit 28: Overflow flag */
+#define ARMV7M_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */
+#define ARMV7M_APSR_Z (1 << 30) /* Bit 30: Zero flag */
+#define ARMV7M_APSR_N (1 << 31) /* Bit 31: Negative, less than flag */
/* Interrupt Program Status Register (IPSR) */
-#define CORTEXM3_IPSR_ISR_SHIFT 0 /* Bits 8-0: ISR number */
-#define CORTEXM3_IPSR_ISR_MASK (0x1ff << CORTEXM3_IPSR_ISR_SHIFT)
+#define ARMV7M_IPSR_ISR_SHIFT 0 /* Bits 8-0: ISR number */
+#define ARMV7M_IPSR_ISR_MASK (0x1ff << ARMV7M_IPSR_ISR_SHIFT)
/* Execution PSR Register (EPSR) */
-#define CORTEXM3_EPSR_ICIIT1_SHIFT 10 /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
-#define CORTEXM3_EPSR_ICIIT1_MASK (3 << CORTEXM3_EPSR_ICIIT1_SHIFT)
-#define CORTEXM3_EPSR_T (1 << 24) /* Bit 24: T-bit */
-#define CORTEXM3_EPSR_ICIIT2_SHIFT 25 /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
-#define CORTEXM3_EPSR_ICIIT2_MASK (3 << CORTEXM3_EPSR_ICIIT2_SHIFT)
+#define ARMV7M_EPSR_ICIIT1_SHIFT 10 /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
+#define ARMV7M_EPSR_ICIIT1_MASK (3 << ARMV7M_EPSR_ICIIT1_SHIFT)
+#define ARMV7M_EPSR_T (1 << 24) /* Bit 24: T-bit */
+#define ARMV7M_EPSR_ICIIT2_SHIFT 25 /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
+#define ARMV7M_EPSR_ICIIT2_MASK (3 << ARMV7M_EPSR_ICIIT2_SHIFT)
/* Save xPSR bits */
-#define CORTEXM3_XPSR_ISR_SHIFT CORTEXM3_IPSR_ISR_SHIFT
-#define CORTEXM3_XPSR_ISR_MASK CORTEXM3_IPSR_ISR_MASK
-#define CORTEXM3_XPSR_ICIIT1_SHIFT CORTEXM3_EPSR_ICIIT1_SHIFT/
-#define CORTEXM3_XPSR_ICIIT1_MASK CORTEXM3_EPSR_ICIIT1_MASK
-#define CORTEXM3_XPSR_T CORTEXM3_EPSR_T
-#define CORTEXM3_XPSR_ICIIT2_SHIFT CORTEXM3_EPSR_ICIIT2_SHIFT
-#define CORTEXM3_XPSR_ICIIT2_MASK CORTEXM3_EPSR_ICIIT2_MASK
-#define CORTEXM3_XPSR_Q CORTEXM3_APSR_Q
-#define CORTEXM3_XPSR_V CORTEXM3_APSR_V
-#define CORTEXM3_XPSR_C CORTEXM3_APSR_C
-#define CORTEXM3_XPSR_Z CORTEXM3_APSR_Z
-#define CORTEXM3_XPSR_N CORTEXM3_APSR_N
+#define ARMV7M_XPSR_ISR_SHIFT ARMV7M_IPSR_ISR_SHIFT
+#define ARMV7M_XPSR_ISR_MASK ARMV7M_IPSR_ISR_MASK
+#define ARMV7M_XPSR_ICIIT1_SHIFT ARMV7M_EPSR_ICIIT1_SHIFT/
+#define ARMV7M_XPSR_ICIIT1_MASK ARMV7M_EPSR_ICIIT1_MASK
+#define ARMV7M_XPSR_T ARMV7M_EPSR_T
+#define ARMV7M_XPSR_ICIIT2_SHIFT ARMV7M_EPSR_ICIIT2_SHIFT
+#define ARMV7M_XPSR_ICIIT2_MASK ARMV7M_EPSR_ICIIT2_MASK
+#define ARMV7M_XPSR_Q ARMV7M_APSR_Q
+#define ARMV7M_XPSR_V ARMV7M_APSR_V
+#define ARMV7M_XPSR_C ARMV7M_APSR_C
+#define ARMV7M_XPSR_Z ARMV7M_APSR_Z
+#define ARMV7M_XPSR_N ARMV7M_APSR_N
/************************************************************************************
* Inline Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H */
+#endif /* __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H */
diff --git a/nuttx/arch/arm/src/cortexm3/svcall.h b/nuttx/arch/arm/src/armv7-m/svcall.h
index 74f7a3438..51b5b9111 100644
--- a/nuttx/arch/arm/src/cortexm3/svcall.h
+++ b/nuttx/arch/arm/src/armv7-m/svcall.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/cortexm3/svcall.h
+ * arch/arm/src/armv7-m/svcall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_assert.c b/nuttx/arch/arm/src/armv7-m/up_assert.c
index 416d763cd..77fd0b596 100644
--- a/nuttx/arch/arm/src/cortexm3/up_assert.c
+++ b/nuttx/arch/arm/src/armv7-m/up_assert.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_assert.c
+ * arch/arm/src/armv7-m/up_assert.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_blocktask.c b/nuttx/arch/arm/src/armv7-m/up_blocktask.c
index 59d1fa04e..e2a612a18 100755
--- a/nuttx/arch/arm/src/cortexm3/up_blocktask.c
+++ b/nuttx/arch/arm/src/armv7-m/up_blocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_blocktask.c
+ * arch/arm/src/armv7-m/up_blocktask.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_copystate.c b/nuttx/arch/arm/src/armv7-m/up_copystate.c
index 8704bc106..a5ad312f5 100644
--- a/nuttx/arch/arm/src/cortexm3/up_copystate.c
+++ b/nuttx/arch/arm/src/armv7-m/up_copystate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_copystate.c
+ * arch/arm/src/armv7-m/up_copystate.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_doirq.c b/nuttx/arch/arm/src/armv7-m/up_doirq.c
index fc2f75c97..ca115c356 100644
--- a/nuttx/arch/arm/src/cortexm3/up_doirq.c
+++ b/nuttx/arch/arm/src/armv7-m/up_doirq.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_doirq.c
+ * arch/arm/src/armv7-m/up_doirq.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_fullcontextrestore.S b/nuttx/arch/arm/src/armv7-m/up_fullcontextrestore.S
index 6709967d7..7795cd23d 100755
--- a/nuttx/arch/arm/src/cortexm3/up_fullcontextrestore.S
+++ b/nuttx/arch/arm/src/armv7-m/up_fullcontextrestore.S
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/cortexm3/up_fullcontextrestore.S
+ * arch/arm/src/armv7-m/up_fullcontextrestore.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_hardfault.c b/nuttx/arch/arm/src/armv7-m/up_hardfault.c
index 0f0c77739..a9eea8103 100644
--- a/nuttx/arch/arm/src/cortexm3/up_hardfault.c
+++ b/nuttx/arch/arm/src/armv7-m/up_hardfault.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_hardfault.c
+ * arch/arm/src/armv7-m/up_hardfault.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_initialstate.c b/nuttx/arch/arm/src/armv7-m/up_initialstate.c
index 094a3adba..6a13f038b 100644
--- a/nuttx/arch/arm/src/cortexm3/up_initialstate.c
+++ b/nuttx/arch/arm/src/armv7-m/up_initialstate.c
@@ -1,7 +1,7 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_initialstate.c
+ * arch/arm/src/armv7-m/up_initialstate.c
*
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -99,7 +99,7 @@ void up_initial_state(_TCB *tcb)
/* Specify thumb mode */
- xcp->regs[REG_XPSR] = CORTEXM3_XPSR_T;
+ xcp->regs[REG_XPSR] = ARMV7M_XPSR_T;
/* If this task is running PIC, then set the PIC base register to the
* address of the allocated D-Space region.
diff --git a/nuttx/arch/arm/src/cortexm3/up_memfault.c b/nuttx/arch/arm/src/armv7-m/up_memfault.c
index cb4c2d739..bbe3f6573 100644
--- a/nuttx/arch/arm/src/cortexm3/up_memfault.c
+++ b/nuttx/arch/arm/src/armv7-m/up_memfault.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_memfault.c
+ * arch/arm/src/armv7-m/up_memfault.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_mpu.c b/nuttx/arch/arm/src/armv7-m/up_mpu.c
index 215f373d4..27936562c 100644
--- a/nuttx/arch/arm/src/cortexm3/up_mpu.c
+++ b/nuttx/arch/arm/src/armv7-m/up_mpu.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_mpu.c
+ * arch/arm/src/armv7-m/up_mpu.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_releasepending.c b/nuttx/arch/arm/src/armv7-m/up_releasepending.c
index 46218cbbe..20b953543 100755
--- a/nuttx/arch/arm/src/cortexm3/up_releasepending.c
+++ b/nuttx/arch/arm/src/armv7-m/up_releasepending.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_releasepending.c
+ * arch/arm/src/armv7-m/up_releasepending.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_reprioritizertr.c b/nuttx/arch/arm/src/armv7-m/up_reprioritizertr.c
index 875fc1d6f..9ac2d1145 100755
--- a/nuttx/arch/arm/src/cortexm3/up_reprioritizertr.c
+++ b/nuttx/arch/arm/src/armv7-m/up_reprioritizertr.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_reprioritizertr.c
+ * arch/arm/src/armv7-m/up_reprioritizertr.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_saveusercontext.S b/nuttx/arch/arm/src/armv7-m/up_saveusercontext.S
index 8fc073a51..c8da07430 100755
--- a/nuttx/arch/arm/src/cortexm3/up_saveusercontext.S
+++ b/nuttx/arch/arm/src/armv7-m/up_saveusercontext.S
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/cortexm3/up_saveusercontext.S
+ * arch/arm/src/armv7-m/up_saveusercontext.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_schedulesigaction.c b/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c
index 879cd6715..f392a08d7 100644
--- a/nuttx/arch/arm/src/cortexm3/up_schedulesigaction.c
+++ b/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c
@@ -1,7 +1,7 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_schedulesigaction.c
+ * arch/arm/src/armv7-m/up_schedulesigaction.c
*
- * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -164,7 +164,7 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
current_regs[REG_PC] = (uint32_t)up_sigdeliver;
current_regs[REG_PRIMASK] = 1;
- current_regs[REG_XPSR] = CORTEXM3_XPSR_T;
+ current_regs[REG_XPSR] = ARMV7M_XPSR_T;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
@@ -198,7 +198,7 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PRIMASK] = 1;
- tcb->xcp.regs[REG_XPSR] = CORTEXM3_XPSR_T;
+ tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T;
}
irqrestore(flags);
diff --git a/nuttx/arch/arm/src/cortexm3/up_sigdeliver.c b/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c
index f05b7ce69..3c340b8d3 100644
--- a/nuttx/arch/arm/src/cortexm3/up_sigdeliver.c
+++ b/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_sigdeliver.c
+ * arch/arm/src/armv7-m/up_sigdeliver.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_svcall.c b/nuttx/arch/arm/src/armv7-m/up_svcall.c
index 7764f9c09..af00a28c1 100644
--- a/nuttx/arch/arm/src/cortexm3/up_svcall.c
+++ b/nuttx/arch/arm/src/armv7-m/up_svcall.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_svcall.c
+ * arch/arm/src/armv7-m/up_svcall.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_switchcontext.S b/nuttx/arch/arm/src/armv7-m/up_switchcontext.S
index 6e60942b3..854f6fa16 100755
--- a/nuttx/arch/arm/src/cortexm3/up_switchcontext.S
+++ b/nuttx/arch/arm/src/armv7-m/up_switchcontext.S
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/cortexm3/up_switchcontext.S
+ * arch/arm/src/armv7-m/up_switchcontext.S
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/cortexm3/up_unblocktask.c b/nuttx/arch/arm/src/armv7-m/up_unblocktask.c
index 8fcc28d83..b29f3d89f 100755
--- a/nuttx/arch/arm/src/cortexm3/up_unblocktask.c
+++ b/nuttx/arch/arm/src/armv7-m/up_unblocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/cortexm3/up_unblocktask.c
+ * arch/arm/src/armv7-m/up_unblocktask.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
diff --git a/nuttx/arch/arm/src/common/up_internal.h b/nuttx/arch/arm/src/common/up_internal.h
index 2992812c3..43c8bbeeb 100644
--- a/nuttx/arch/arm/src/common/up_internal.h
+++ b/nuttx/arch/arm/src/common/up_internal.h
@@ -82,7 +82,7 @@
* a referenced is passed to get the state from the TCB.
*/
-#ifdef CONFIG_ARCH_CORTEXM3
+#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# define up_savestate(regs) up_copystate(regs, (uint32_t*)current_regs)
# define up_restorestate(regs) (current_regs = regs)
#else
@@ -121,7 +121,7 @@ extern uint32_t g_heapbase;
/* Address of the saved user stack pointer */
#if CONFIG_ARCH_INTERRUPTSTACK > 3
-# ifdef CONFIG_ARCH_CORTEXM3
+#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
extern void g_intstackbase;
# else
extern uint32_t g_userstack;
@@ -180,14 +180,14 @@ extern void up_sigdeliver(void);
extern void up_irqinitialize(void);
extern void up_maskack_irq(int irq);
-#ifdef CONFIG_ARCH_CORTEXM3
+#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
extern uint32_t *up_doirq(int irq, uint32_t *regs);
extern int up_svcall(int irq, FAR void *context);
extern int up_hardfault(int irq, FAR void *context);
extern int up_memfault(int irq, FAR void *context);
-#else /* CONFIG_ARCH_CORTEXM3 */
+#else /* CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
extern void up_doirq(int irq, uint32_t *regs);
#ifdef CONFIG_PAGING
@@ -202,7 +202,7 @@ extern void up_prefetchabort(uint32_t *regs);
extern void up_syscall(uint32_t *regs);
extern void up_undefinedinsn(uint32_t *regs);
-#endif /* CONFIG_ARCH_CORTEXM3 */
+#endif /* CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
extern void up_vectorundefinsn(void);
extern void up_vectorswi(void);
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
index b8a81f1e4..15cdad24a 100755
--- a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
+++ b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/kinetis/kinetis_memorymap.h
*
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -61,7 +61,7 @@
# define KINETIS_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
# define KINETIS_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
# define KINETIS_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
-#define KINETIS_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
+#define KINETIS_CORTEXM4_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define KINETIS_SCS_BASE 0xe000e000
#define KINETIS_DEBUGMCU_BASE 0xe0042000
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_irq.c b/nuttx/arch/arm/src/lm3s/lm3s_irq.c
index 915ce3d13..b026a8303 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_irq.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_irq.c
@@ -320,7 +320,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
-#ifdef CONFIG_CORTEXM3_MPU
+#ifdef CONFIG_ARMV7M_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LM3S_IRQ_MEMFAULT);
#endif
@@ -329,7 +329,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(LM3S_IRQ_NMI, lm3s_nmi);
-#ifndef CONFIG_CORTEXM3_MPU
+#ifndef CONFIG_ARMV7M_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault);
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c
index cf3467833..577ec6747 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c
@@ -308,7 +308,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
-#ifdef CONFIG_CORTEXM3_MPU
+#ifdef CONFIG_ARMV7M_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LPC17_IRQ_MEMFAULT);
#endif
@@ -317,7 +317,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(LPC17_IRQ_NMI, lpc17_nmi);
-#ifndef CONFIG_CORTEXM3_MPU
+#ifndef CONFIG_ARMV7M_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault);
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
index 59a6fd51e..da69f1481 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
@@ -61,7 +61,7 @@
# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
-#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
+#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define LPC17_SCS_BASE 0xe000e000
#define LPC17_DEBUGMCU_BASE 0xe0042000
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_irq.c b/nuttx/arch/arm/src/sam3u/sam3u_irq.c
index 228be0f1f..ecfb68b4a 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_irq.c
+++ b/nuttx/arch/arm/src/sam3u/sam3u_irq.c
@@ -301,7 +301,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
-#ifdef CONFIG_CORTEXM3_MPU
+#ifdef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
up_enable_irq(SAM3U_IRQ_MEMFAULT);
#endif
@@ -310,7 +310,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(SAM3U_IRQ_NMI, sam3u_nmi);
-#ifndef CONFIG_CORTEXM3_MPU
+#ifndef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(SAM3U_IRQ_BUSFAULT, sam3u_busfault);
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h
index cc81db5f7..6b7e2e737 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h
@@ -125,7 +125,7 @@
#define STM32_FSMC_BASE 0xa0000000
-/* Other registers -- see cortexm3/nvic.h for standard Cortex-M3 registers in this
+/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
* address range
*/
diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c
index b27f5448e..40c0c5bc3 100644
--- a/nuttx/arch/arm/src/stm32/stm32_irq.c
+++ b/nuttx/arch/arm/src/stm32/stm32_irq.c
@@ -335,7 +335,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
-#ifdef CONFIG_CORTEXM3_MPU
+#ifdef CONFIG_ARMV7M_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
up_enable_irq(STM32_IRQ_MEMFAULT);
#endif
@@ -344,7 +344,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(STM32_IRQ_NMI, stm32_nmi);
-#ifndef CONFIG_CORTEXM3_MPU
+#ifndef CONFIG_ARMV7M_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault);
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-13 04:45:18 +0000