diff options
Diffstat (limited to 'nuttx/configs/open1788/tools/open1788.cfg')
| -rwxr-xr-x | nuttx/configs/open1788/tools/open1788.cfg | 46 |
1 files changed, 45 insertions, 1 deletions
diff --git a/nuttx/configs/open1788/tools/open1788.cfg b/nuttx/configs/open1788/tools/open1788.cfg index 9c251b4e9..54f699216 100755 --- a/nuttx/configs/open1788/tools/open1788.cfg +++ b/nuttx/configs/open1788/tools/open1788.cfg @@ -29,6 +29,7 @@ set CPUROMSIZE 0x80000 set CCLK 12000 ### From /usr/local/share/openocd/scripts/targets/lpc17xx.cfg +### With additions to set the operating frequency to 120MHz # Common LPC17xx logic # LPC17xx chips support both JTAG and SWD transports. @@ -100,6 +101,49 @@ flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ adapter_khz 1000 $_TARGETNAME configure -event reset-init { + echo "Going to 120MHz" + + # PLL0CON: Disable PLL + mww 0x400FC080 0x00000000 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # CLKSEL: internal 12MHz RC oscillator Div 1. + mww 0x400FC104 0x00000001 + # CLKSRCSEL: Clock source = internal 12MHz RC oscillator + mww 0x400FC10C 0x00000000 + + # PLL0CFG: M=10,P=1 -> PLL=240 MHz + mww 0x400FC084 0x00000009 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # PLL0CON: Enable PLL + mww 0x400FC080 0x00000001 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + sleep 50 + + # PLL0CON: Connect PLL + # CCLKSEL=PLLED(240MHz)/2 (=120 MHz) + mww 0x400FC104 0x00000102 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # Dividing CPU clock by 8 should be pretty conservative + # + # + adapter_khz 1500 + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select # "User Flash Mode" where interrupt vectors are _not_ remapped, # and reside in flash instead). @@ -114,7 +158,7 @@ $_TARGETNAME configure -event reset-init { # # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user - mww 0x4ba00477 0x01 + mww 0x400FC040 0x01 } # if srst is not fitted use VECTRESET to |