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### From /usr/local/share/openocd/scripts/interface/olimex-arm-usb-ocd.cfg
#
# Olimex ARM-USB-OCD
#
# http://www.olimex.com/dev/arm-usb-ocd.html
#
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG A"
ft2232_layout olimex-jtag
ft2232_vid_pid 0x15ba 0x0003
### From /usr/local/share/openocd/scripts/targets/lpc1788.cfg
# NXP LPC1788 Cortex-M3 with 512kB Flash and 96kB Local On-Chip SRAM
# remember to place in the same folder as lpc17xx.cfg
set CHIPNAME lpc1788
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x18000
set CPUROMSIZE 0x80000
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 12000
### From /usr/local/share/openocd/scripts/targets/lpc17xx.cfg
### With additions to set the operating frequency to 120MHz
# Common LPC17xx logic
# LPC17xx chips support both JTAG and SWD transports.
# JTAG is hard-coded in this configuration
# Adapt based on what transport is active.
# source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
error "_CHIPNAME not set"
}
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
set _CCLK $CCLK
} else {
set _CCLK 4000
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
error "_CPUTAPID not set"
}
if { [info exists CPURAMSIZE] } {
set _CPURAMSIZE $CPURAMSIZE
} else {
error "_CPURAMSIZE not set"
}
if { [info exists CPUROMSIZE] } {
set _CPUROMSIZE $CPUROMSIZE
} else {
error "_CPUROMSIZE not set"
}
#delays on reset lines
adapter_nsrst_delay 500
jtag_ntrst_delay 500
# Use of JTAG is hard-coded
#swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
# The LPC17xx devices have 32/64/128/256/512kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
adapter_khz 1000
$_TARGETNAME configure -event reset-init {
echo "Going to 120MHz"
# PLL0CON: Disable PLL
mww 0x400FC080 0x00000000
# PLLFEED
mww 0x400FC08C 0x000000AA
# PLLFEED
mww 0x400FC08C 0x00000055
# CLKSEL: internal 12MHz RC oscillator Div 1.
mww 0x400FC104 0x00000001
# CLKSRCSEL: Clock source = internal 12MHz RC oscillator
mww 0x400FC10C 0x00000000
# PLL0CFG: M=10,P=1 -> PLL=240 MHz
mww 0x400FC084 0x00000009
# PLLFEED
mww 0x400FC08C 0x000000AA
# PLLFEED
mww 0x400FC08C 0x00000055
# PLL0CON: Enable PLL
mww 0x400FC080 0x00000001
# PLLFEED
mww 0x400FC08C 0x000000AA
# PLLFEED
mww 0x400FC08C 0x00000055
sleep 50
# PLL0CON: Connect PLL
# CCLKSEL=PLLED(240MHz)/2 (=120 MHz)
mww 0x400FC104 0x00000102
# PLLFEED
mww 0x400FC08C 0x000000AA
# PLLFEED
mww 0x400FC08C 0x00000055
# Dividing CPU clock by 8 should be pretty conservative
#
#
adapter_khz 1500
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
# Bit Symbol Value Description Reset
# value
# 0 MAP Memory map control. 0
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
# 1 User mode. The on-chip Flash memory is mapped to address 0.
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
#
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
mww 0x400FC040 0x01
}
# if srst is not fitted use VECTRESET to
# perform a soft reset - SYSRESETREQ is not supported
cortex_m3 reset_config vectreset
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