diff options
Diffstat (limited to 'nuttx')
-rwxr-xr-x | nuttx/arch/arm/src/lpc31xx/lpc31_evntrtr.h | 16 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h | 110 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h | 160 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h | 16 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h | 192 | ||||
-rwxr-xr-x | nuttx/configs/stm3210e-eval/README.txt | 9 |
6 files changed, 493 insertions, 10 deletions
diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_evntrtr.h b/nuttx/arch/arm/src/lpc31xx/lpc31_evntrtr.h index aa24c755b..b35c35a8a 100755 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_evntrtr.h +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_evntrtr.h @@ -58,17 +58,17 @@ #define LPC31_EVNTRTR_NOUTPUTS 5 /* Outputs o=0-4 (incl CGU Wakeup) */ #define LPC31_EVNTRTR_NEVENTS (32*LPC31_EVNTRTR_NBANKS) -#define _B(b) ((b)<<2) /* Maps bank number 0-3 to word offset */ -#define _O(o) ((o)<<5) /* Maps output to bank group offset */ -#define _OB(o,b) (_O(o)+_B(b)) /* Mqpw output and bank to word offset */ +#define _B(b) ((b)<<2) /* Maps bank number 0-3 to word offset */ +#define _O(o) ((o)<<5) /* Maps output to bank group offset */ +#define _OB(o,b) (_O(o)+_B(b)) /* Mqpw output and bank to word offset */ -#define EVNTRTR_EVENT(bank,bit) ((bank)<<5|bit) /* Makes a event number from a bank and bit */ -#define EVNTRTR_BANK(e) ((e)>>5) /* Maps a event to a bank */ -#define EVNTRTR_BIT(e) ((e)&0x1f) /* Maps a event to a bit */ +#define EVNTRTR_EVENT(bank,bit) ((bank)<<5|bit) /* Makes a event number from a bank and bit */ +#define EVNTRTR_BANK(e) ((e)>>5) /* Maps a event to a bank */ +#define EVNTRTR_BIT(e) ((e)&0x1f) /* Maps a event to a bit */ /* EVNTRTR register offsets (with respect to the EVNTRTR base) ******************************************/ - /* 0x0000-0x0bff: Reserved */ + /* 0x0000-0x0bff: Reserved */ #define LPC31_EVNTRTR_PEND_OFFSET(b) (0x0c00+_B(b)) /* Input event pending */ #define LPC31_EVNTRTR_INTCLR_OFFSET(b) (0x0c20+_B(b)) /* Input event clear */ #define LPC31_EVNTRTR_INTSET_OFFSET(b) (0x0c40+_B(b)) /* Input event set */ @@ -79,7 +79,7 @@ #define LPC31_EVNTRTR_ATR_OFFSET(b) (0x0ce0+_B(b)) /* Input event activation type */ #define LPC31_EVNTRTR_RSR_OFFSET(b) (0x0d20+_B(b)) /* Input event raw status */ #define LPC31_EVNTRTR_INTOUT_OFFSET 0x0d40 /* State of interrupt output pins */ - /* 0x0e00-0x0ffc: Reserved */ + /* 0x0e00-0x0ffc: Reserved */ #define LPC31_EVNTRTR_INTOUTPEND_OFFSET(o,b) (0x1000+_OB(o,b)) /* Interrupt output 'o' pending */ #define LPC31_EVNTRTR_CGUWKUPPEND_OFFSET(b) (0x1000+_OB(4,b)) /* cgu_wakeup pending */ #define LPC31_EVNTRTR_INTOUTMASK_OFFSET(o,b) (0x1400+_OB(o,b)) /* Interrupt output 'o' mask */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h new file mode 100644 index 000000000..43b623c87 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h @@ -0,0 +1,110 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/chip/lpc43_aes.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* The AES is controlled through a set of simple API calls located in the LPC43xx + * ROM. This value holds the pointer to the AES driver table. + */ + +#define LPC43_ROM_AES_DRIVER_TABLE LPC43_ROM_DRIVER_TABLE2 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +enum lpc43_aescmd_e +{ + AES_API_CMD_ENCODE_ECB = 0, + AES_API_CMD_DECODE_ECB = 1, + AES_API_CMD_ENCODE_CBC = 2, + AES_API_CMD_DECODE_CBC = 3 +}; + +struct lpc43_aes_s +{ + /* Initialize the AES engine */ + + void (*aes_Init)(void); + + /* Offset 0x04 -- Defines AES engine operation mode. See enum lpc43_aescmd_e */ + + unsigned int (*aes_SetMode)(unsigned int cmd); + + /* Load 128-bit AES user keys */ + + void (*aes_LoadKey1)(void); + void (*aes_LoadKey2)(void); + + /* Loads randomly generated key in AES engine. To update the RNG and load a new + * random number, use the API call otp_GenRand before aes_LoadKeyRNG. + */ + + void (*aes_LoadKeyRNG)(void); + + /* Loads 128-bit AES software defined user key (16 bytes) */ + + void (*aes_LoadKeySW)(unsigned char *key); + + /* Loads 128-bit AES initialization vector (16 bytes) */ + + void (*aes_LoadIV_SW)(unsigned char *iv); + + /* Loads 128-bit AES IC specific initialization vector, which is used to decrypt + * a boot image. + */ + + void (*aes_LoadIV_IC)(void); +}; + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h new file mode 100644 index 000000000..faacfb418 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h @@ -0,0 +1,160 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define LPC43_EVNTRTR_HILO_OFFSET 0x0000 /* Level configuration register */ +#define LPC43_EVNTRTR_EDGE_OFFSET 0x0004 /* Edge configuration */ + +#define LPC43_EVNTRTR_CLREN_OFFSET 0x0fd8 /* Clear event enable register */ +#define LPC43_EVNTRTR_SETEN_OFFSET 0x0fdc /* Set event enable register */ +#define LPC43_EVNTRTR_STATUS_OFFSET 0x0fe0 /* Event Status register */ +#define LPC43_EVNTRTR_ENABLE_OFFSET 0x0fe4 /* Event Enable register */ +#define LPC43_EVNTRTR_CLRSTAT_OFFSET 0x0fe8 /* Clear event status register */ +#define LPC43_EVNTRTR_SETSTAT_OFFSET 0x0fec /* Set event status register */ + +/* Register Addresses ***************************************************************/ + +#define LPC43_EVNTRTR_HILO (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_HILO_OFFSET) +#define LPC43_EVNTRTR_EDGE (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_EDGE_OFFSET) + +#define LPC43_EVNTRTR_CLREN (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_CLREN_OFFSET) +#define LPC43_EVNTRTR_SETEN (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_SETEN_OFFSET) +#define LPC43_EVNTRTR_STATUS (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_STATUS_OFFSET) +#define LPC43_EVNTRTR_ENABLE (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_ENABLE_OFFSET) +#define LPC43_EVNTRTR_CLRSTAT (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_CLRSTAT_OFFSET) +#define LPC43_EVNTRTR_SETSTAT (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_SETSTAT_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* Event router inputs. Bit settings common to all registers */ + +#define EVNTRTR_SOURCE_WAKEUP0 0 /* WAKEUP0 pin */ +#define EVNTRTR_SOURCE_WAKEUP1 1 /* WAKEUP1 pin */ +#define EVNTRTR_SOURCE_WAKEUP2 2 /* WAKEUP2 pin */ +#define EVNTRTR_SOURCE_WAKEUP3 3 /* WAKEUP3 pin */ +#define EVNTRTR_SOURCE_ATIMER 4 /* Alarm timer interrupt */ +#define EVNTRTR_SOURCE_RTC 5 /* RTC interrupt and event recorder/monitor interrupt */ +#define EVNTRTR_SOURCE_BOD 6 /* BOD trip level 1interrupt */ +#define EVNTRTR_SOURCE_WWDT 7 /* WWDT interrupt */ +#define EVNTRTR_SOURCE_ETHERNET 8 /* Ethernet wake-up packet indicator */ +#define EVNTRTR_SOURCE_USB0 9 /* USB0 wake-up request signal */ +#define EVNTRTR_SOURCE_USB1 10 /* USB1 AHB_NEED_CLK signal */ +#define EVNTRTR_SOURCE_SDMMC 11 /* SD/MMC interrupt */ +#define EVNTRTR_SOURCE_CAN 12 /* C_CAN0 | C_CAN1 interrupt */ +#define EVNTRTR_SOURCE_TIM2 13 /* Combined timer output 2 (SCT output 2 | TIMER0 Ch2) */ +#define EVNTRTR_SOURCE_TIM6 14 /* Combined timer output 6 (SCT output 6 | TIMER1 Ch2) */ +#define EVNTRTR_SOURCE_QEI 15 /* QEI interrupt */ +#define EVNTRTR_SOURCE_TIM14 16 /* Combined timer output 14 (SCT output 14 | TIMER3 Ch2) */ + /* 17-18: Reserved */ +#define EVNTRTR_SOURCE_RESET 19 /* Reset event */ + +#define EVNTRTR_WAKEUP0 (1 << EVNTRTR_SOURCE_WAKEUP0) +#define EVNTRTR_WAKEUP1 (1 << EVNTRTR_SOURCE_WAKEUP1) +#define EVNTRTR_WAKEUP2 (1 << EVNTRTR_SOURCE_WAKEUP2) +#define EVNTRTR_WAKEUP3 (1 << EVNTRTR_SOURCE_WAKEUP3) +#define EVNTRTR_ATIMER (1 << EVNTRTR_SOURCE_ATIMER) +#define EVNTRTR_RTC (1 << EVNTRTR_SOURCE_RTC) +#define EVNTRTR_BOD (1 << EVNTRTR_SOURCE_BOD) +#define EVNTRTR_WWDT (1 << EVNTRTR_SOURCE_WWDT) +#define EVNTRTR_ETH (1 << EVNTRTR_SOURCE_ETHERNET) +#define EVNTRTR_USB0 (1 << EVNTRTR_SOURCE_USB0) +#define EVNTRTR_USB1 (1 << EVNTRTR_SOURCE_USB1) +#define EVNTRTR_SDMMC (1 << EVNTRTR_SOURCE_SDMMC) +#define EVNTRTR_CAN (1 << EVNTRTR_SOURCE_CAN) +#define EVNTRTR_TIM2 (1 << EVNTRTR_SOURCE_TIM2) +#define EVNTRTR_TIM6 (1 << EVNTRTR_SOURCE_TIM6) +#define EVNTRTR_QEI (1 << EVNTRTR_SOURCE_QEI) +#define EVNTRTR_TIM14 (1 << EVNTRTR_SOURCE_TIM14) +#define EVNTRTR_RESET (1 << EVNTRTR_SOURCE_RESET) + +/* Level configuration register */ + +#define EVNTRTR_HILO(n) (1 << (n)) + +/* Edge configuration */ + +#define EVNTRTR_EDGE(n) (1 << (n)) + +/* Clear event enable register */ + +#define EVNTRTR_CLREN(n) (1 << (n)) + +/* Set event enable register */ + +#define EVNTRTR_SETEN(n) (1 << (n)) + +/* Event Status register */ + +#define EVNTRTR_STATUS(n) (1 << (n)) + +/* Event Enable register */ + +#define EVNTRTR_ENABLE(n) (1 << (n)) + +/* Clear event status register */ + +#define EVNTRTR_CLRSTAT(n) (1 << (n)) + +/* Set event status register */ + +#define EVNTRTR_SETSTAT(n) (1 << (n)) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h index ab069bde7..162fb714a 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc43xx/chip.h + * arch/arm/src/lpc43xx/chip/lpc43_memorymap.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -73,6 +73,18 @@ #define LPC43_EXTMEM_CS2_BASE (LPC43_LOCSRAM_BASE + 0x0e000000) #define LPC43_EXTMEM_CS3_BASE (LPC43_LOCSRAM_BASE + 0x0f000000) +/* ROM Driver Table */ + +#define LPC43_ROM_DRIVER_TABLE (LPC43_ROM_BASE+0x00000100) +#define LPC43_ROM_DRIVER_TABLE0 (LPC43_ROM_DRIVER_TABLE+0x0000) +#define LPC43_ROM_DRIVER_TABLE1 (LPC43_ROM_DRIVER_TABLE+0x0004) +#define LPC43_ROM_DRIVER_TABLE2 (LPC43_ROM_DRIVER_TABLE+0x0008) +#define LPC43_ROM_DRIVER_TABLE3 (LPC43_ROM_DRIVER_TABLE+0x000c) +#define LPC43_ROM_DRIVER_TABLE4 (LPC43_ROM_DRIVER_TABLE+0x0010) +#define LPC43_ROM_DRIVER_TABLE5 (LPC43_ROM_DRIVER_TABLE+0x0014) +#define LPC43_ROM_DRIVER_TABLE6 (LPC43_ROM_DRIVER_TABLE+0x0018) +#define LPC43_ROM_DRIVER_TABLE7 (LPC43_ROM_DRIVER_TABLE+0x001c) + /* AHB SRAM */ #define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE) @@ -112,7 +124,7 @@ #define LPC43_BACKUP_BASE (LPC43_RTCPERIPH_BASE + 0x00001000) #define LPC43_PWRMODE_BASE (LPC43_RTCPERIPH_BASE + 0x00002000) #define LPC43_CREG_BASE (LPC43_RTCPERIPH_BASE + 0x00003000) -#define LPC43_EVROUTER_BASE (LPC43_RTCPERIPH_BASE + 0x00004000) +#define LPC43_EVNTRTR_BASE (LPC43_RTCPERIPH_BASE + 0x00004000) #define LPC43_OTPC_BASE (LPC43_RTCPERIPH_BASE + 0x00005000) #define LPC43_RTC_BASE (LPC43_RTCPERIPH_BASE + 0x00006000) diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h new file mode 100644 index 000000000..5b4ac6c7c --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h @@ -0,0 +1,192 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/chip/lpc43_otp.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define LPC43_OTP_MEM00_OFFSET 0x0010 /* General purpose OTP memory 0, word 0 */ +#define LPC43_OTP_MEM01_OFFSET 0x0014 /* General purpose OTP memory 0, word 1 */ +#define LPC43_OTP_MEM02_OFFSET 0x0018 /* General purpose OTP memory 0, word 2 */ +#define LPC43_OTP_MEM03_OFFSET 0x001c /* General purpose OTP memory 0, word 3 */ + +#define LPC43_OTP_MEM10_OFFSET 0x0020 /* General purpose OTP memory 1, word 0 */ +#define LPC43_OTP_MEM11_OFFSET 0x0024 /* General purpose OTP memory 1, word 1 */ +#define LPC43_OTP_MEM12_OFFSET 0x0028 /* General purpose OTP memory 1, word 2 */ +#define LPC43_OTP_MEM13_OFFSET 0x002c /* General purpose OTP memory 1, word 3 */ + +#define LPC43_OTP_MEM20_OFFSET 0x0034 /* General purpose OTP memory 2, word 0 */ +#define LPC43_OTP_MEM21_OFFSET 0x0038 /* General purpose OTP memory 2, word 1 */ +#define LPC43_OTP_MEM22_OFFSET 0x003c /* General purpose OTP memory 2, word 2 */ + +#define LPC43_OTP_AES00_OFFSET 0x0010 /* AES key 0, word 0 */ +#define LPC43_OTP_AES01_OFFSET 0x0014 /* AES key 0, word 1 */ +#define LPC43_OTP_AES02_OFFSET 0x0018 /* AES key 0, word 2 */ +#define LPC43_OTP_AES03_OFFSET 0x001c /* AES key 0, word 3 */ + +#define LPC43_OTP_AES10_OFFSET 0x0020 /* AES key 1, word 0 */ +#define LPC43_OTP_AES11_OFFSET 0x0024 /* AES key 1, word 1 */ +#define LPC43_OTP_AES12_OFFSET 0x0028 /* AES key 1, word 2 */ +#define LPC43_OTP_AES13_OFFSET 0x002c /* AES key 1, word 3 */ + +#define LPC43_OTP_CCD_OFFSET 0x0030 /* Customer control data */ +#define LPC43_OTP_USBID_OFFSET 0x0034 /* USB ID */ + +/* Register Addresses ***************************************************************/ + +#define LPC43_OTP_MEM00 (LPC43_OTPC_BASE+LPC43_OTP_MEM00_OFFSET) +#define LPC43_OTP_MEM01 (LPC43_OTPC_BASE+LPC43_OTP_MEM01_OFFSET) +#define LPC43_OTP_MEM02 (LPC43_OTPC_BASE+LPC43_OTP_MEM02_OFFSET) +#define LPC43_OTP_MEM03 (LPC43_OTPC_BASE+LPC43_OTP_MEM03_OFFSET) + +#define LPC43_OTP_MEM10 (LPC43_OTPC_BASE+LPC43_OTP_MEM10_OFFSET) +#define LPC43_OTP_MEM11 (LPC43_OTPC_BASE+LPC43_OTP_MEM11_OFFSET) +#define LPC43_OTP_MEM12 (LPC43_OTPC_BASE+LPC43_OTP_MEM12_OFFSET) +#define LPC43_OTP_MEM13 (LPC43_OTPC_BASE+LPC43_OTP_MEM13_OFFSET) + +#define LPC43_OTP_MEM20 (LPC43_OTPC_BASE+LPC43_OTP_MEM20_OFFSET) +#define LPC43_OTP_MEM21 (LPC43_OTPC_BASE+LPC43_OTP_MEM21_OFFSET) +#define LPC43_OTP_MEM22 (LPC43_OTPC_BASE+LPC43_OTP_MEM22_OFFSET) + +#define LPC43_OTP_AES00 (LPC43_OTPC_BASE+LPC43_OTP_AES00_OFFSET) +#define LPC43_OTP_AES01 (LPC43_OTPC_BASE+LPC43_OTP_AES01_OFFSET) +#define LPC43_OTP_AES02 (LPC43_OTPC_BASE+LPC43_OTP_AES02_OFFSET) +#define LPC43_OTP_AES03 (LPC43_OTPC_BASE+LPC43_OTP_AES03_OFFSET) + +#define LPC43_OTP_AES10 (LPC43_OTPC_BASE+LPC43_OTP_AES10_OFFSET) +#define LPC43_OTP_AES11 (LPC43_OTPC_BASE+LPC43_OTP_AES11_OFFSET) +#define LPC43_OTP_AES12 (LPC43_OTPC_BASE+LPC43_OTP_AES12_OFFSET) +#define LPC43_OTP_AES13 (LPC43_OTPC_BASE+LPC43_OTP_AES13_OFFSET) + +#define LPC43_OTP_CCD (LPC43_OTPC_BASE+LPC43_OTP_CCD_OFFSET) +#define LPC43_OTP_USBID (LPC43_OTPC_BASE+LPC43_OTP_USBID_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* Customer control data */ + /* Bits 0-22: Reserved */ +#define OTP_CCD_USBID (1 << 23) /* Bit 23: USB ID enable */ + /* Bit 24: Reserved */ +#define OPT_CCD_BOOTSRC_SHIFT (25) /* Bits 25-28: Boot source selection in OTP */ +#define OPT_CCD_BOOTSRC_MASK (15 << OPT_CCD_BOOTSRC_SHIFT) +# define OPT_CCD_BOOTSRC_EXT (0 << OPT_CCD_BOOTSRC_SHIFT) /* External pins */ +# define OPT_CCD_BOOTSRC_UART0 (1 << OPT_CCD_BOOTSRC_SHIFT) /* UART0 */ +# define OPT_CCD_BOOTSRC_EMC8 (3 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 8-bit */ +# define OPT_CCD_BOOTSRC_EMC16 (4 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 16-bit */ +# define OPT_CCD_BOOTSRC_EMC32 (5 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 32-bit */ +# define OPT_CCD_BOOTSRC_USB0 (6 << OPT_CCD_BOOTSRC_SHIFT) /* USB0 */ +# define OPT_CCD_BOOTSRC_USB1 (7 << OPT_CCD_BOOTSRC_SHIFT) /* USB1 */ +# define OPT_CCD_BOOTSRC_SPI (8 << OPT_CCD_BOOTSRC_SHIFT) /* SPI (via SSP) */ +# define OPT_CCD_BOOTSRC_UART3 (9 << OPT_CCD_BOOTSRC_SHIFT) /* UART3 */ + /* Bits 29-30: Reserved */ +#define OTP_CCD_JTAGDIS (1 << 31) /* Bit 31: JTAG disable */ + +/* USB ID */ + +#define OTP_USBID_VID_SHIFT (0) /* Bits 0-15: USB vendor ID */ +#define OTP_USBID_VID_MASK (0xffff << OTP_USBID_VID_SHIFT) +#define OTP_USBID_PID_SHIFT (0) /* Bits 16-31: USB product ID */ +#define OTP_USBID_PID_MASK (0xffff << OTP_USBID_PID_SHIFT) + +/* OTP API *************************************************************************/ +/* The AES is controlled through a set of simple API calls located in the LPC43xx + * ROM. This value holds the pointer to the OTP driver table. + */ + +#define LPC43_ROM_OTP_DRIVER_TABLE LPC43_ROM_DRIVER_TABLE1 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +struct lpc43_otp_s +{ + /* Initializes the OTP controller */ + + unsigned int (*otp_Init)(void); + + /* Programs boot source */ + + unsigned int (*otp_ProgBootSrc)(unsigned int src); + + /* JTAG disable. This command disables JTAG only when the device is AES capable. */ + + unsigned int (*otp_ProgJTAGDis)(void); + + /* Programs USB_ID */ + + unsigned int (*otp_ProgUSBID)(unsigned int pid, unsigned int vid); + + /* Reserved */ + + void *reserved[3]; + + /* Program the general purpose OTP memories. Use only if the device is not AES + * capable. + */ + + unsigned int (*otp_ProgGP0)(unsigned int data, unsigned int mask); + unsigned int (*otp_ProgGP1)(unsigned int data, unsigned int mask); + unsigned int (*otp_ProgGP2)(unsigned int data, unsigned int mask); + + /* Program AES keys. 16 byte keys are expected. */ + + unsigned int (*otp_ProgKey1)(unsigned char *key); + unsigned int (*otp_ProgKey2)(unsigned char *key); + + /* Generate new random number using the hardware Random Number Generator (RNG). */ + + unsigned int (*otp_GenRand)(void); +}; + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H */ diff --git a/nuttx/configs/stm3210e-eval/README.txt b/nuttx/configs/stm3210e-eval/README.txt index aea32dffb..c46f73811 100755 --- a/nuttx/configs/stm3210e-eval/README.txt +++ b/nuttx/configs/stm3210e-eval/README.txt @@ -805,6 +805,15 @@ Where <subdir> is one of the following: CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin + pm: + -- + This is a configuration that is used to test STM32 power management, i.e., + to test that the board can go into lower and lower states of power usage + as a result of inactivity. This configuration is based on the nsh2 + configuration with modifications for testing power management. + + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + RIDE ---- This configuration builds a trivial bring-up binary. It is |