Finish serial drivers

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2738 42af7a65-404d-4744-a932-0658087f49c3

6 files changed, 439 insertions, 282 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h
index 52c6b45f2..e23e6e964 100755
--- a/nuttx/arch/arm/src/lpc17xx/chip.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip.h
@@ -51,6 +51,7 @@
 #if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
 #  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
 #  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -63,6 +64,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1767)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
 #  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
 #  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -75,6 +77,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1766)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
 #  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
 #  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -87,6 +90,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1765)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
 #  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
 #  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
@@ -99,8 +103,9 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1764)
 #  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
 #  define LPC17_NUSBHOST        0  /* No USB host controller */
 #  define LPC17_NUSBOTG         0  /* No USB OTG controller */
@@ -111,6 +116,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1759)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
 #  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
 #  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
@@ -123,6 +129,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1758)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
 #  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
 #  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -135,8 +142,9 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1756)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -147,8 +155,9 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1754)
 #  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -159,8 +168,9 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1752)
 #  define LPC17_FLASH_SIZE      (64*1024) /* 65Kb */
 #  define LPC17_SRAM_SIZE       (16*1024) /* 16Kb */
-#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
+#  define LPC17_CPUSRAM_SIZE    (16*1024)
+#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        0  /* No USB host controller */
 #  define LPC17_NUSBOTG         0  /* No USB OTG controller */
@@ -171,8 +181,9 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1751)
 #  define LPC17_FLASH_SIZE      (32*1024) /* 32Kb */
 #  define LPC17_SRAM_SIZE       (8*1024)  /*  8Kb */
-#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
+#  define LPC17_CPUSRAM_SIZE    (8*1024)
+#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        0  /* No USB host controller */
 #  define LPC17_NUSBOTG         0  /* No USB OTG controller */
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
index 3fee53018..bcb701407 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
@@ -49,15 +49,29 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
+#include "lpc17_memorymap.h"
+
 /****************************************************************************
  * Private Definitions
  ****************************************************************************/
 
-#if CONFIG_DRAM_END > (LPC17_SRAM_BASE+LPC17_SRAM_SIZE)
-#  error "CONFIG_DRAM_END is beyond the end of CPU SRAM"
+/* Configuration ************************************************************/
+
+#if CONFIG_DRAM_START != LPC17_SRAM_BASE
+#  warning "CONFIG_DRAM_START is not at LPC17_SRAM_BASE"
+#  undef CONFIG_DRAM_START
+#  undef CONFIG_DRAM_END
+#  define CONFIG_DRAM_START LPC17_SRAM_BASE
+#  define CONFIG_DRAM_END  (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE)
+#endif
+
+#if CONFIG_DRAM_SIZE > LPC17_CPUSRAM_SIZE
+#  warning "CONFIG_DRAM_SIZE is larger than the size of CPU SRAM"
+#  undef CONFIG_DRAM_SIZE
 #  undef CONFIG_DRAM_END
-#  define CONFIG_DRAM_END (LPC17_SRAM_BASE+LPC17_SRAM_SIZE)
-#elif CONFIG_DRAM_END < (LPC17_SRAM_BASE+LPC17_SRAM_SIZE)
+#  define CONFIG_DRAM_SIZE LPC17_CPUSRAM_SIZE
+#  define CONFIG_DRAM_END (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE)
+#elif CONFIG_DRAM_SIZE < LPC17_CPUSRAM_SIZE
 #  warning "CONFIG_DRAM_END is before end of CPU SRAM... not all of CPU SRAM used"
 #endif
 
@@ -67,7 +81,9 @@
 #  endif
 #else
 #  if CONFIG_MM_REGIONS > 1
-#    warning "CONFIG_MM_REGIONS > 1: This MCH has no AHB SRAM Bank0"
+#    warning "CONFIG_MM_REGIONS > 1: This MCU has no AHB SRAM Bank0"
+#    undef CONFIG_MM_REGIONS
+#    define CONFIG_MM_REGIONS 1
 #  endif
 #endif
 
@@ -77,7 +93,9 @@
 #  endif
 #else
 #  if CONFIG_MM_REGIONS > 2
-#    warning "CONFIG_MM_REGIONS > 2: This MCH has no AHB SRAM Bank1"
+#    warning "CONFIG_MM_REGIONS > 2: This MCU has no AHB SRAM Bank1"
+#    undef CONFIG_MM_REGIONS
+#    define CONFIG_MM_REGIONS 2
 #  endif
 #endif
 
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h
index b6e9ce3b0..e5321acef 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h
@@ -169,6 +169,15 @@
 #define GPIO_PIN31           (31 << GPIO_PIN_SHIFT)
 
 /* GPIO pin definitions *************************************************************/
+/* NOTE that functions have a alternate pins that can be selected.  These alternates
+ * are identified with a numerica suffix like _1, _2, or _3.  Your board.h file
+ * should select the correct alternative for your board by including definitions
+ * such as:
+ *
+ * #define GPIO_UART1_RXD GPIO_UART1_RXD_1
+ *
+ * (without the suffix)
+ */
 
 #define GPIO_CAN1_RD_1     (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0)
 #define GPIO_UART3_TXD_1   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0)
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c
index f8e76e6e3..e567bc1c2 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c
@@ -264,7 +264,7 @@ void up_lowputc(char ch)
  *   console.  Its purpose is to get the console output availabe as soon
  *   as possible.
  *
- *   The UART0/2/3 peripherals are configured using the following registers:
+ *   The UART0/1/2/3 peripherals are configured using the following registers:
  *   1. Power: In the PCONP register, set bits PCUART0/1/2/3.
  *      On reset, UART0 and UART 1 are enabled (PCUART0 = 1 and PCUART1 = 1)
  *      and UART2/3 are disabled (PCUART1 = 0 and PCUART3 = 0).
@@ -289,142 +289,104 @@ void up_lowputc(char ch)
 void lpc17_lowsetup(void)
 {
 #ifdef HAVE_UART
-
-#if 0
   uint32_t regval;
 
-  /* Step 1: Enable power for all selected UARTs */
+  /* Step 1: Enable power for all console UART and disable power for
+   * other UARTs
+   */
 
-  regval = getreg32(LPC17_SYSCON_PCONP);
-  regval &= ~(SYSCON_PCONP_PCUART0|SYSCON_PCONP_PCUART1|SYSCON_PCONP_PCUART2|SYSCON_PCONP_PCUART3)
-#ifdef CONFIG_LPC17_UART0
+  regval  = getreg32(LPC17_SYSCON_PCONP);
+  regval &= ~(SYSCON_PCONP_PCUART0|SYSCON_PCONP_PCUART1|
+              SYSCON_PCONP_PCUART2|SYSCON_PCONP_PCUART3)
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
   regval |= SYSCON_PCONP_PCUART0;
-#endif
-#ifdef CONFIG_LPC17_UART1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
   regval |= SYSCON_PCONP_PCUART1;
-#endif
-#ifdef CONFIG_LPC17_UART2
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
   regval |= SYSCON_PCONP_PCUART2;
-#endif
-#ifdef CONFIG_LPC17_UART3
+#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
   regval |= SYSCON_PCONP_PCUART3;
 #endif
   putreg32(regval, LPC17_SYSCON_PCONP);
 
-/* Step 2: Enable peripheral clocking for all selected UARTs */
-
-#define SYSCON_PCLKSET_MASK           (3)
-
-#define SYSCON_PCLKSEL0_UART0_SHIFT   (6)         /* Bits 6-7: Peripheral clock UART0 */
-#define SYSCON_PCLKSEL0_UART0_MASK    (3 << SYSCON_PCLKSEL0_UART0_MASK)
-#define SYSCON_PCLKSEL0_UART1_SHIFT   (8)         /* Bits 8-9: Peripheral clock UART1 */
-#define SYSCON_PCLKSEL0_UART1_MASK    (3 << SYSCON_PCLKSEL0_UART1_SHIFT)
-
-
-#define SYSCON_PCLKSEL1_UART2_SHIFT   (16)        /* Bits 16-17: Peripheral clock UART2 */
-#define SYSCON_PCLKSEL1_UART2_MASK    (3 << SYSCON_PCLKSEL1_UART2_SHIFT)
-#define SYSCON_PCLKSEL1_UART3_SHIFT   (18)        /* Bits 18-19: Peripheral clock UART3 */
-#define SYSCON_PCLKSEL1_UART3_MASK    (3 << SYSCON_PCLKSEL1_UART3_SHIFT)
-
-  /* Configure UART pins for all selected UARTs */
-
-#define GPIO_UART0_TXD     (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
-#define GPIO_UART0_RXD     (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3
-
-#define GPIO_UART1_TXD_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15)
-#define GPIO_UART1_RXD_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16)
-#define GPIO_UART1_CTS_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17)
-#define GPIO_UART1_DCD_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
-#define GPIO_UART1_DSR_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19)
-#define GPIO_UART1_DTR_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20)
-#define GPIO_UART1_RI_1    (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21)
-#define GPIO_UART1_RTS_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22)
-
-#define GPIO_UART1_TXD_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0)
-#define GPIO_UART1_RXD_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1)
-#define GPIO_UART1_CTS_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2)
-#define GPIO_UART1_DCD_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3)
-#define GPIO_UART1_DSR_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4)
-#define GPIO_UART1_DTR_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5)
-#define GPIO_UART1_RI_2    (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6)
-#define GPIO_UART1_RTS_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7)
-
-#define GPIO_UART2_TXD_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
-#define GPIO_UART2_RXD_1   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11)
-#define GPIO_UART2_TXD_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8)
-#define GPIO_UART2_RXD_2   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9)
-
-#define GPIO_UART3_TXD_1   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0)
-#define GPIO_UART3_RXD_1   (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1)
-#define GPIO_UART3_TXD_2   (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25)
-#define GPIO_UART3_RXD_2   (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26)
-#define GPIO_UART3_TXD_3   (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28)
-#define GPIO_UART3_RXD_3     (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29)
-
-
-#ifdef CONFIG_LPC17_UART0
-  (void)lpc17_configgpio(GPIO_UART0_RXD);
-  (void)lpc17_configgpio(GPIO_UART0_TXD);
-  (void)lpc17_configgpio(GPIO_UART0_CTS);
-  (void)lpc17_configgpio(GPIO_UART0_RTS);
-#endif
-#ifdef CONFIG_LPC17_UART1
-  (void)lpc17_configgpio(GPIO_UART1_RXD);
-  (void)lpc17_configgpio(GPIO_UART1_TXD);
-  (void)lpc17_configgpio(GPIO_UART1_CTS);
-  (void)lpc17_configgpio(GPIO_UART1_RTS);
-#endif
-#ifdef CONFIG_LPC17_UART2
-  (void)lpc17_configgpio(GPIO_UART2_RXD);
-  (void)lpc17_configgpio(GPIO_UART2_TXD);
-  (void)lpc17_configgpio(GPIO_UART2_CTS);
-  (void)lpc17_configgpio(GPIO_UART2_RTS);
-#endif
-#ifdef CONFIG_LPC17_UART3
-  (void)lpc17_configgpio(GPIO_UART3_RXD);
-  (void)lpc17_configgpio(GPIO_UART3_TXD);
-  (void)lpc17_configgpio(GPIO_UART3_CTS);
-  (void)lpc17_configgpio(GPIO_UART3_RTS);
-#endif
+/* Step 2: Enable peripheral clocking for the console UART and disable
+ * clocking for all other UARTs
+ */
 
-#ifdef GPIO_CONSOLE_RXD
+  regval = getreg32(LPC17_SYSCON_PCLKSEL0);
+  regval &= SYSCON_PCLKSEL0_UART1_MASK;
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL0_UART0_SHIFT);
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+  regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL0_UART1_SHIFT);
 #endif
-#ifdef GPIO_CONSOLE_TXD
-  (void)lpc17_configgpio(GPIO_CONSOLE_TXD);
+  putreg32(regval, LPC17_SYSCON_PCLKSEL0);
+
+  regval = getreg32(LPC17_SYSCON_PCLKSEL1);
+  regval &= SYSCON_PCLKSEL0_UART2_MASK;
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART2_SHIFT);
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+  regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART23_SHIFT);
 #endif
-#ifdef GPIO_CONSOLE_CTS
-  (void)lpc17_configgpio(GPIO_CONSOLE_CTS);
+  putreg32(regval, LPC17_SYSCON_PCLKSEL1);
+
+  /* Configure UART pins for the selected CONSOLE */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  lpc17_configgpio(GPIO_UART0_TXD);
+  lpc17_configgpio(GPIO_UART0_RXD);
+  irqrestore(flags);
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+  lpc17_configgpio(GPIO_UART1_TXD);
+  lpc17_configgpio(GPIO_UART1_RXD);
+#ifdef CONFIG_UART0_FLOWCONTROL
+  lpc17_configgpio(GPIO_UART1_CTS);
+  lpc17_configgpio(GPIO_UART1_DCD);
+  lpc17_configgpio(GPIO_UART1_DSR);
+  lpc17_configgpio(GPIO_UART1_DTR);
+  lpc17_configgpio(GPIO_UART1_RI);
+  lpc17_configgpio(GPIO_UART1_RTS);
 #endif
-#ifdef GPIO_CONSOLE_RTS
-  (void)lpc17_configgpio(GPIO_CONSOLE_RTS);
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+  lpc17_configgpio(GPIO_UART2_TXD);
+  lpc17_configgpio(GPIO_UART2_RXD);
+  irqrestore(flags);
+#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
+  lpc17_configgpio(GPIO_UART3_TXD);
+  lpc17_configgpio(GPIO_UART3_RXD);
 #endif
 
   /* Configure the console (only) */
+
 #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
-  /* Reset and disable receiver and transmitter */
 
-  putreg32((UART_CR_RSTRX|UART_CR_RSTTX|UART_CR_RXDIS|UART_CR_TXDIS),
-           CONSOLE_BASE+LPC17_UART_CR_OFFSET);
+  /* Clear fifos */
+
+  putreg32(UART_FCR_RXRST|UART_FCR_TXRST, CONSOLE_BASE+LPC17_UART_FCR_OFFSET);
+
+  /* Set trigger */
+
+  putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC17_UART_FCR_OFFSET);
 
-  /* Disable all interrupts */
+  /* Set up the LCR and set DLAB=1*/
 
-  putreg32(0xffffffff, CONSOLE_BASE+LPC17_UART_IDR_OFFSET);
+  putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+LPC17_UART_LCR_OFFSET);
 
-  /* Set up the mode register */
+  /* Set the BAUD divisor */
 
-  putreg32(MR_VALUE, CONSOLE_BASE+LPC17_UART_MR_OFFSET);
+  putreg32(CONSOLE_DL >> 8, CONSOLE_BASE+LPC17_UART_DLM_OFFSET);
+  putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE+LPC17_UART_DLL_OFFSET);
 
-  /* Configure the console baud */
+  /* Clear DLAB */
 
-  putreg32(((LPC17_MCK_FREQUENCY + (LPC17_CONSOLE_BAUD << 3))/(LPC17_CONSOLE_BAUD << 4)),
-           CONSOLE_BASE+LPC17_UART_BRGR_OFFSET);
+  putreg32(CONSOLE_LCR_VALUE, LPC17_UART_LCR_OFFSET);
 
-  /* Enable receiver & transmitter */
+  /* Configure the FIFOs */
 
-  putreg32((UART_CR_RXEN|UART_CR_TXEN),
-           CONSOLE_BASE+LPC17_UART_CR_OFFSET);
+  putreg32(UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN,
+           CONSOLE_BASE+LPC17_UART_FCR_OFFSET);
 #endif
-#endif /* 0 */
 #endif /* HAVE_UART */
 }
 
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c
index 8df4d5249..3ef2cbf6a 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c
@@ -47,10 +47,13 @@
 #include <string.h>
 #include <errno.h>
 #include <debug.h>
+
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
 #include <nuttx/serial.h>
+
 #include <arch/serial.h>
+#include <arch/board/board.h>
 
 #include "chip.h"
 #include "up_arch.h"
@@ -426,9 +429,9 @@ static uart_dev_t g_uart3port =
 #  endif
 #endif
 
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
 
 /****************************************************************************
  * Name: up_serialin
@@ -491,6 +494,287 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
   up_serialout(priv, LPC17_UART_LCR_OFFSET, lcr);
 }
 
+/************************************************************************************
+ * Name: lpc17_uartcclkdiv
+ *
+ * Descrption:
+ *   Select a CCLK divider to produce the UART PCLK.  The stratey is to select the
+ *   smallest divisor that results in an solution within range of the 16-bit
+ *   DLM and DLL divisor:
+ *
+ *     PCLK = CCLK / divisor
+ *     BAUD = PCLK / (16 * DL)
+ *
+ *   Ignoring the fractional divider for now.
+ *
+ *   NOTE:  This is an inline function.  If a typical optimization level is used and
+ *   a constant is provided for the desired frequency, then most of the following
+ *   logic will be optimized away.
+ *
+ ************************************************************************************/
+
+static inline uint8_t lpc17_uartcclkdiv(uint32_t baud)
+{
+  /* Ignoring the fractional divider, the BAUD is given by:
+   *
+   *   BAUD = PCLK / (16 * DL), or
+   *   DL   = PCLK / BAUD / 16
+   *
+   * Where:
+   *
+   *   PCLK = CCLK / divisor.
+   *
+   * Check divisor == 1.  This works if the upper limit is met	
+   *
+   *   DL < 0xffff, or
+   *   PCLK / BAUD / 16 < 0xffff, or
+   *   CCLK / BAUD / 16 < 0xffff, or
+   *   CCLK < BAUD * 0xffff * 16
+   *   BAUD > CCLK / 0xffff / 16
+   *
+   * And the lower limit is met (we can't allow DL to get very close to one).
+   *
+   *   DL >= MinDL
+   *   CCLK / BAUD / 16 >= MinDL, or
+   *   BAUD <= CCLK / 16 / MinDL
+   */
+
+  if (baud < (LPC17_CCLK / 16 / UART_MINDL ))
+    {
+      return SYSCON_PCLKSEL_CCLK;
+    }
+   
+  /* Check divisor == 2.  This works if:
+   *
+   *   2 * CCLK / BAUD / 16 < 0xffff, or
+   *   BAUD > CCLK / 0xffff / 8
+   *
+   * And
+   *
+   *   2 * CCLK / BAUD / 16 >= MinDL, or
+   *   BAUD <= CCLK / 8 / MinDL
+   */
+
+  else if (baud < (LPC17_CCLK / 8 / UART_MINDL ))
+    {
+      return SYSCON_PCLKSEL_CCLK2;
+    }
+
+  /* Check divisor == 4.  This works if:
+   *
+   *   4 * CCLK / BAUD / 16 < 0xffff, or
+   *   BAUD > CCLK / 0xffff / 4
+   *
+   * And
+   *
+   *   4 * CCLK / BAUD / 16 >= MinDL, or
+   *   BAUD <= CCLK / 4 / MinDL 
+   */
+
+  else if (baud < (LPC17_CCLK / 4 / UART_MINDL ))
+    {
+      return SYSCON_PCLKSEL_CCLK4;
+    }
+
+  /* Check divisor == 8.  This works if:
+   *
+   *   8 * CCLK / BAUD / 16 < 0xffff, or
+   *   BAUD > CCLK / 0xffff / 2
+   *
+   * And
+   *
+   *   8 * CCLK / BAUD / 16 >= MinDL, or
+   *   BAUD <= CCLK / 2 / MinDL 
+   */
+
+  else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL )) */
+    {
+      return SYSCON_PCLKSEL_CCLK8;
+    }
+}
+
+/************************************************************************************
+ * Name: lpc17_uart0config, uart1config, uart2config, nad uart3config
+ *
+ * Descrption:
+ *   Configure the UART.  UART0/1/2/3 peripherals are configured using the following
+ *   registers:
+ *
+ *   1. Power: In the PCONP register, set bits PCUART0/1/2/3.
+ *      On reset, UART0 and UART 1 are enabled (PCUART0 = 1 and PCUART1 = 1)
+ *      and UART2/3 are disabled (PCUART1 = 0 and PCUART3 = 0).
+ *   2. Peripheral clock: In the PCLKSEL0 register, select PCLK_UART0 and
+ *      PCLK_UART1; in the PCLKSEL1 register, select PCLK_UART2 and PCLK_UART3.
+ *   3. Pins: Select UART pins through the PINSEL registers and pin modes
+ *      through the PINMODE registers. UART receive pins should not have
+ *      pull-down resistors enabled.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_LPC17_UART0
+static inline void lpc17_uart0config(uint8_t clkdiv)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power on UART0 */
+
+  flags   = irqsave();
+  regval  = getreg32(LPC17_SYSCON_PCONP);
+  regval |= ~SYSCON_PCONP_PCUART0;
+  putreg32(regval, LPC17_SYSCON_PCONP);
+
+  /* Step 2: Enable clocking on UART */
+
+  regval = getreg32(LPC17_SYSCON_PCLKSEL0);
+  regval &= ~SYSCON_PCLKSEL0_UART0_MASK;
+  regval |= ((uint32_t)clkdiv << SYSCON_PCLKSEL0_UART0_SHIFT);
+  putreg32(regval, LPC17_SYSCON_PCLKSEL0);
+
+  /* Step 3: Configure I/O pins */
+
+  lpc17_configgpio(GPIO_UART0_TXD);
+  lpc17_configgpio(GPIO_UART0_RXD);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_LPC17_UART1
+static inline void lpc17_uart1config(uint8_t clkdiv)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power on UART1 */
+
+  flags   = irqsave();
+  regval  = getreg32(LPC17_SYSCON_PCONP);
+  regval |= ~SYSCON_PCONP_PCUART1;
+  putreg32(regval, LPC17_SYSCON_PCONP);
+
+  /* Step 2: Enable clocking on UART */
+
+  regval = getreg32(LPC17_SYSCON_PCLKSEL0);
+  regval &= ~SYSCON_PCLKSEL0_UART1_MASK;
+  regval |= ((uint32_t)clkdiv << SYSCON_PCLKSEL0_UART1_SHIFT);
+  putreg32(regval, LPC17_SYSCON_PCLKSEL0);
+
+  /* Step 3: Configure I/O pins */
+
+  lpc17_configgpio(GPIO_UART1_TXD);
+  lpc17_configgpio(GPIO_UART1_RXD);
+#ifdef CONFIG_UART0_FLOWCONTROL
+  lpc17_configgpio(GPIO_UART1_CTS);
+  lpc17_configgpio(GPIO_UART1_DCD);
+  lpc17_configgpio(GPIO_UART1_DSR);
+  lpc17_configgpio(GPIO_UART1_DTR);
+  lpc17_configgpio(GPIO_UART1_RI);
+  lpc17_configgpio(GPIO_UART1_RTS);
+#endif
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_LPC17_UART2
+static inline void lpc17_uart2config(uint8_t clkdiv)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power on UART2 */
+
+  flags   = irqsave();
+  regval  = getreg32(LPC17_SYSCON_PCONP);
+  regval |= SYSCON_PCONP_PCUART2;
+  putreg32(regval, LPC17_SYSCON_PCONP);
+
+  /* Step 2: Enable clocking on UART */
+
+  regval = getreg32(LPC17_SYSCON_PCLKSEL1);
+  regval &= ~SYSCON_PCLKSEL0_UART2_MASK;
+  regval |= ((uint32_t)clkdiv << SYSCON_PCLKSEL1_UART2_SHIFT);
+  putreg32(regval, LPC17_SYSCON_PCLKSEL1);
+
+  /* Step 3: Configure I/O pins */
+
+  lpc17_configgpio(GPIO_UART2_TXD);
+  lpc17_configgpio(GPIO_UART2_RXD);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_LPC17_UART3
+static inline void lpc17_uart3config(uint8_t clkdiv)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power on UART3 */
+
+  flags   = irqsave();
+  regval  = getreg32(LPC17_SYSCON_PCONP);
+  regval |= ~SYSCON_PCONP_PCUART3;
+  putreg32(regval, LPC17_SYSCON_PCONP);
+
+  /* Step 2: Enable clocking on UART */
+
+  regval = getreg32(LPC17_SYSCON_PCLKSEL1);
+  regval &= ~SYSCON_PCLKSEL0_UART3_MASK;
+  regval |= ((uint32_t)clkdiv << SYSCON_PCLKSEL1_UART3_SHIFT);
+  putreg32(regval, LPC17_SYSCON_PCLKSEL1);
+
+  /* Step 3: Configure I/O pins */
+
+  lpc17_configgpio(GPIO_UART3_TXD);
+  lpc17_configgpio(GPIO_UART3_RXD);
+  irqrestore(flags);
+};
+#endif
+
+/************************************************************************************
+ * Name: lpc17_uartdl
+ *
+ * Descrption:
+ *   Select a divider to produce the BAUD from the UART PCLK.
+ *
+ *     BAUD = PCLK / (16 * DL), or
+ *     DL   = PCLK / BAUD / 16
+ *
+ *   Ignoring the fractional divider for now.
+ *
+ ************************************************************************************/
+
+static inline uint32_t lpc17_uartdl(uint32_t baud, uint8_t divcode)
+{
+  uint32_t num;
+
+  switch (divcode)
+    {
+
+    case SYSCON_PCLKSEL_CCLK4:   /* PCLK_peripheral = CCLK/4 */
+      num = (LPC17_CCLK / 4);
+      break;
+
+    case SYSCON_PCLKSEL_CCLK:    /* PCLK_peripheral = CCLK */
+      num = LPC17_CCLK;
+      break;
+
+    case SYSCON_PCLKSEL_CCLK2:   /* PCLK_peripheral = CCLK/2 */
+      num = (LPC17_CCLK / 2);
+      break;
+
+    case SYSCON_PCLKSEL_CCLK8:   /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */
+    default:
+      num = (LPC17_CCLK / 8);
+      break;
+    }
+  return num / (baud << 4);
+}
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
 /****************************************************************************
  * Name: up_setup
  *
@@ -952,30 +1236,42 @@ static bool up_txempty(struct uart_dev_s *dev)
  *   serial console will be available during bootup.  This must be called
  *   before up_serialinit.
  *
- *   NOTE: Power, clocking, and pin configuration was performed in
- *   up_lowsetup() very, early in the boot sequence.
+ *   NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
+ *   very early in the boot sequence.
  *
  ****************************************************************************/
 
 void up_earlyserialinit(void)
 {
-  /* Disable all UARTS */
+  /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
 
-#ifdef TTYS0_DEV
-  TTYS0_DEV.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART0_BAUD);
-  up_disableuartint(TTYS0_DEV.priv, NULL);
+#ifdef CONFIG_LPC17_UART0
+  g_uart0priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART0_BAUD);
+#ifndef CONFIG_UART0_SERIAL_CONSOLE
+  lpc17_uart0config(g_uart0priv.cclkdiv);
 #endif
-#ifdef TTYS1_DEV
-  TTYS1_DEV.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART1_BAUD);
-  up_disableuartint(TTYS1_DEV.priv, NULL);
+  up_disableuartint(g_uart0priv.priv, NULL);
 #endif
-#ifdef TTYS2_DEV
-  TTYS2_DEV.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART2_BAUD);
-  up_disableuartint(TTYS2_DEV.priv, NULL);
+#ifdef CONFIG_LPC17_UART1
+  g_uart1priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART1_BAUD);
+#ifndef CONFIG_UART1_SERIAL_CONSOLE
+  lpc17_uart1config(g_uart1priv.cclkdiv);
 #endif
-#ifdef TTYS3_DEV
-  TTYS3_DEV.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART3_BAUD);
-  up_disableuartint(TTYS3_DEV.priv, NULL);
+  up_disableuartint(g_uart1priv.priv, NULL);
+#endif
+#ifdef CONFIG_LPC17_UART2
+  g_uart2priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART2_BAUD);
+#ifndef CONFIG_UART2_SERIAL_CONSOLE
+  lpc17_uart2config(g_uart2priv.cclkdiv);
+#endif
+  up_disableuartint(g_uart2priv.priv, NULL);
+#endif
+#ifdef CONFIG_LPC17_UART3
+  g_uart3priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART3_BAUD);
+#ifndef CONFIG_UART3_SERIAL_CONSOLE
+  lpc17_uart3config(g_uart3priv.cclkdiv);
+#endif
+  up_disableuartint(g_uart3priv.priv, NULL);
 #endif
 
   /* Configuration whichever one is the console */
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h
index 64ee62a65..b293aba0c 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h
@@ -112,145 +112,6 @@
  ************************************************************************************/

 

 /************************************************************************************

- * Name: lpc17_uartcclkdiv

- *

- * Descrption:

- *   Select a CCLK divider to produce the UART PCLK.  The stratey is to select the

- *   smallest divisor that results in an solution within range of the 16-bit

- *   DLM and DLL divisor:

- *

- *     PCLK = CCLK / divisor

- *     BAUD = PCLK / (16 * DL)

- *

- *   Ignoring the fractional divider for now.

- *

- *   NOTE:  This is an inline function.  If a typical optimization level is used and

- *   a constant is provided for the desired frequency, then most of the following

- *   logic will be optimized away.

- *

- ************************************************************************************/

-

-static inline uint8_t lpc17_uartcclkdiv(uint32_t baud)

-{

-  /* Ignoring the fractional divider, the BAUD is given by:

-   *

-   *   BAUD = PCLK / (16 * DL), or

-   *   DL   = PCLK / BAUD / 16

-   *

-   * Where:

-   *

-   *   PCLK = CCLK / divisor.

-   *

-   * Check divisor == 1.  This works if the upper limit is met	

-   *

-   *   DL < 0xffff, or

-   *   PCLK / BAUD / 16 < 0xffff, or

-   *   CCLK / BAUD / 16 < 0xffff, or

-   *   CCLK < BAUD * 0xffff * 16

-   *   BAUD > CCLK / 0xffff / 16

-   *

-   * And the lower limit is met (we can't allow DL to get very close to one).

-   *

-   *   DL >= MinDL

-   *   CCLK / BAUD / 16 >= MinDL, or

-   *   BAUD <= CCLK / 16 / MinDL

-   */

-

-  if (baud < (LPC17_CCLK / 16 / UART_MINDL ))

-    {

-      return SYSCON_PCLKSEL_CCLK;

-    }

-   

-  /* Check divisor == 2.  This works if:

-   *

-   *   2 * CCLK / BAUD / 16 < 0xffff, or

-   *   BAUD > CCLK / 0xffff / 8

-   *

-   * And

-   *

-   *   2 * CCLK / BAUD / 16 >= MinDL, or

-   *   BAUD <= CCLK / 8 / MinDL

-   */

-

-  else if (baud < (LPC17_CCLK / 8 / UART_MINDL ))

-    {

-      return SYSCON_PCLKSEL_CCLK2;

-    }

-

-  /* Check divisor == 4.  This works if:

-   *

-   *   4 * CCLK / BAUD / 16 < 0xffff, or

-   *   BAUD > CCLK / 0xffff / 4

-   *

-   * And

-   *

-   *   4 * CCLK / BAUD / 16 >= MinDL, or

-   *   BAUD <= CCLK / 4 / MinDL 

-   */

-

-  else if (baud < (LPC17_CCLK / 4 / UART_MINDL ))

-    {

-      return SYSCON_PCLKSEL_CCLK4;

-    }

-

-  /* Check divisor == 8.  This works if:

-   *

-   *   8 * CCLK / BAUD / 16 < 0xffff, or

-   *   BAUD > CCLK / 0xffff / 2

-   *

-   * And

-   *

-   *   8 * CCLK / BAUD / 16 >= MinDL, or

-   *   BAUD <= CCLK / 2 / MinDL 

-   */

-

-  else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL )) */

-    {

-      return SYSCON_PCLKSEL_CCLK8;

-    }

-}

-

-/************************************************************************************

- * Name: lpc17_uartdl

- *

- * Descrption:

- *   Select a divider to produce the BAUD from the UART PCLK.

- *

- *     BAUD = PCLK / (16 * DL), or

- *     DL   = PCLK / BAUD / 16

- *

- *   Ignoring the fractional divider for now.

- *

- ************************************************************************************/

-

-static inline uint32_t lpc17_uartdl(uint32_t baud, uint8_t divcode)

-{

-  uint32_t num;

-

-  switch (divcode)

-    {

-

-    case SYSCON_PCLKSEL_CCLK4:   /* PCLK_peripheral = CCLK/4 */

-      num = (LPC17_CCLK / 4);

-      break;

-

-    case SYSCON_PCLKSEL_CCLK:    /* PCLK_peripheral = CCLK */

-      num = LPC17_CCLK;

-      break;

-

-    case SYSCON_PCLKSEL_CCLK2:   /* PCLK_peripheral = CCLK/2 */

-      num = (LPC17_CCLK / 2);

-      break;

-

-    case SYSCON_PCLKSEL_CCLK8:   /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */

-    default:

-      num = (LPC17_CCLK / 8);

-      break;

-    }

-  return num / (baud << 4);

-}

-

-/************************************************************************************

  * Public Functions

  ************************************************************************************/