Add config for 2G Engineering Nucleus LPC1768 board

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2728 42af7a65-404d-4744-a932-0658087f49c3

7 files changed, 802 insertions, 20 deletions

diff --git a/nuttx/arch/arm/include/lpc17xx/irq.h b/nuttx/arch/arm/include/lpc17xx/irq.h
index 37b775994..f9d8de546 100755
--- a/nuttx/arch/arm/include/lpc17xx/irq.h
+++ b/nuttx/arch/arm/include/lpc17xx/irq.h
@@ -85,13 +85,13 @@
                                                        * Capture 0-1 */
 #define LPC17_IRQ_TMR3          (LPC17_IRQ_EXTINT+4)  /* Timer 3 Match 0-3
                                                        * Capture 0-1 */
-#define LPC17_IRQ_UART0         (LPC17_IRQ_EXTINT+5)  /* UART0 Rx Line Status (RLS)
+#define LPC17_IRQ_UART0         (LPC17_IRQ_EXTINT+5)  /* UART 0 Rx Line Status (RLS)
                                                        * Transmit Holding Register Empty (THRE)
                                                        * Rx Data Available (RDA)
                                                        * Character Time-out Indicator (CTI)
                                                        * End of Auto-Baud (ABEO)
                                                        * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART1         (LPC17_IRQ_EXTINT+6)  /* UART1 Rx Line Status (RLS)
+#define LPC17_IRQ_UART1         (LPC17_IRQ_EXTINT+6)  /* UART 1 Rx Line Status (RLS)
                                                        * Transmit Holding Register Empty (THRE)
                                                        * Rx Data Available (RDA)
                                                        * Character Time-out Indicator (CTI)
@@ -128,10 +128,10 @@
 #define LPC17_IRQ_PLL0          (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
 #define LPC17_IRQ_RTC           (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
                                                        * Alarm (RTCALF) */
-#define LPC17_IRQ_EINT0         (LPC17_IRQ_EXTINT+18) /* External Interrupt External Interrupt 0 (EINT0) */
-#define LPC17_IRQ_EINT1         (LPC17_IRQ_EXTINT+19) /* External Interrupt External Interrupt 1 (EINT1) */
-#define LPC17_IRQ_EINT2         (LPC17_IRQ_EXTINT+20) /* External Interrupt External Interrupt 2 (EINT2) */
-#define LPC17_IRQ_EINT3         (LPC17_IRQ_EXTINT+21) /* External Interrupt External Interrupt 3 (EINT3)
+#define LPC17_IRQ_EINT0         (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
+#define LPC17_IRQ_EINT1         (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
+#define LPC17_IRQ_EINT2         (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
+#define LPC17_IRQ_EINT3         (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
                                                        * Note: EINT3 channel is shared with GPIO interrupts */
 #define LPC17_IRQ_ADC           (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
 #define LPC17_IRQ_BOD           (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
diff --git a/nuttx/arch/arm/src/lpc17xx/Make.defs b/nuttx/arch/arm/src/lpc17xx/Make.defs
new file mode 100755
index 000000000..b6b1276e2
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc17xx/Make.defs
@@ -0,0 +1,63 @@
+############################################################################
+# arch/arm/src/lpc17xx/Make.defs
+#
+#   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# The start-up, "head", file
+
+HEAD_ASRC	= lpc17_vectors.S
+
+# Common ARM and Cortex-M3 files
+
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
+		  up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c \
+		  up_initialstate.c up_interruptcontext.c up_modifyreg8.c \
+		  up_modifyreg16.c up_modifyreg32.c up_releasepending.c \
+		  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
+		  up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \
+		  up_hardfault.c up_svcall.c
+
+# Required SAM3U files
+
+CHIP_ASRCS	=
+CHIP_CSRCS	= lpc17_start.c
+#CHIP_CSRCS	= lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpioirq.c \
+#		  lpc17_irq.c lpc17_lowputc.c lpc17_pio.c lpc17_serial.c \
+#		  lpc17_start.c lpc17_timerisr.c
+
+# Configuration-dependent SAM3U files
+
+ifeq ($(CONFIG_LPC17_DMA),y)
+CHIP_CSRCS	+= lpc17_dmac.c
+endif
diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h
index c743b7ffd..0a921c4cf 100755
--- a/nuttx/arch/arm/src/lpc17xx/chip.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip.h
@@ -48,7 +48,7 @@
 
 /* Get customizations for each supported chip */
 
-#if defined(CONFIG_LPC17XX_LPC1769) || defined(CONFIG_LPC17XX_LPC1768)
+#if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -58,7 +58,7 @@
 #  define LPC17_NCAN            2  /* Two CAN controllers */
 #  define LPC17_NI2S            1  /* One I2S module */
 #  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1767)
+#elif defined(CONFIG_ARCH_CHIP_LPC1767)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -68,7 +68,7 @@
 #  define LPC17_NCAN            0  /* No CAN controllers */
 #  define LPC17_NI2S            1  /* One I2S module */
 #  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1766)
+#elif defined(CONFIG_ARCH_CHIP_LPC1766)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -78,7 +78,7 @@
 #  define LPC17_NCAN            2  /* Two CAN controllers */
 #  define LPC17_NI2S            1  /* One I2S module */
 #  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1765)
+#elif defined(CONFIG_ARCH_CHIP_LPC1765)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
@@ -88,7 +88,7 @@
 #  define LPC17_NCAN            2  /* Two CAN controllers */
 #  define LPC17_NI2S            1  /* One I2S module */
 #  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1764)
+#elif defined(CONFIG_ARCH_CHIP_LPC1764)
 #  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -98,7 +98,7 @@
 #  define LPC17_NCAN            2  /* Two CAN controllers */
 #  define LPC17_NI2S            0  /* No I2S modules */
 #  define LPC17_NDAC            0  /* No DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1759)
+#elif defined(CONFIG_ARCH_CHIP_LPC1759)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
@@ -108,7 +108,7 @@
 #  define LPC17_NCAN            2  /* Two CAN controllers */
 #  define LPC17_NI2S            1  /* One I2S module */
 #  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1758)
+#elif defined(CONFIG_ARCH_CHIP_LPC1758)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
@@ -118,7 +118,7 @@
 #  define LPC17_NCAN            2  /* Two CAN controllers */
 #  define LPC17_NI2S            1  /* One I2S module */
 #  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1756)
+#elif defined(CONFIG_ARCH_CHIP_LPC1756)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
@@ -128,7 +128,7 @@
 #  define LPC17_NCAN            2  /* Two CAN controllers */
 #  define LPC17_NI2S            1  /* One I2S module */
 #  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1754)
+#elif defined(CONFIG_ARCH_CHIP_LPC1754)
 #  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
@@ -138,7 +138,7 @@
 #  define LPC17_NCAN            1  /* One CAN controller */
 #  define LPC17_NI2S            0  /* No I2S modules */
 #  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1752)
+#elif defined(CONFIG_ARCH_CHIP_LPC1752)
 #  define LPC17_FLASH_SIZE      (64*1024) /* 65Kb */
 #  define LPC17_SRAM_SIZE       (16*1024) /* 16Kb */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
@@ -148,7 +148,7 @@
 #  define LPC17_NCAN            1  /* One CAN controller */
 #  define LPC17_NI2S            0  /* No I2S modules */
 #  define LPC17_NDAC            0  /* No DAC module */
-#elif defined(CONFIG_LPC17XX_LPC1751)
+#elif defined(CONFIG_ARCH_CHIP_LPC1751)
 #  define LPC17_FLASH_SIZE      (32*1024) /* 32Kb */
 #  define LPC17_SRAM_SIZE       (8*1024)  /*  8Kb */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
@@ -166,7 +166,7 @@
  * file for the proper setup
  */
 
-#include "lpc17xx_memorymap.h"
+#include "lpc17_memorymap.h"
 
 /************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h
new file mode 100755
index 000000000..13807509f
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h
@@ -0,0 +1,219 @@
+/************************************************************************************
+ * arch/arm/src/lpc17xx/lpc17_internal.h
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_INTERNAL_H
+#define __ARCH_ARM_SRC_LPC17XX_LPC17_INTERNAL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Configuration ********************************************************************/
+
+/* Bit-encoded input to lpc17_configgpio() ******************************************/
+
+/* GPIO pin definitions *************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: lpc17_clockconfig
+ *
+ * Description:
+ *   Called to initialize the LPC17XX.  This does whatever setup is needed to put the
+ *   MCU in a usable state.  This includes the initialization of clocking using the
+ *   settings in board.h.
+ *
+ ************************************************************************************/
+
+EXTERN void lpc17_clockconfig(void);
+
+/************************************************************************************
+ * Name: lpc17_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Performs low level initialization
+ *   including setup of the console UART.  This UART done early so that the serial
+ *   console is available for debugging very early in the boot sequence.
+ *
+ ************************************************************************************/
+
+EXTERN void lpc17_lowsetup(void);
+
+/************************************************************************************
+ * Name: lpc17_gpioirqinitialize
+ *
+ * Description:
+ *   Initialize logic to support a second level of interrupt decoding for GPIO pins.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+EXTERN void lpc17_gpioirqinitialize(void);
+#else
+#  define lpc17_gpioirqinitialize()
+#endif
+
+/************************************************************************************
+ * Name: lpc17_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ************************************************************************************/
+
+EXTERN int lpc17_configgpio(uint16_t cfgset);
+
+/************************************************************************************
+ * Name: lpc17_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ************************************************************************************/
+
+EXTERN void lpc17_gpiowrite(uint16_t pinset, bool value);
+
+/************************************************************************************
+ * Name: lpc17_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ************************************************************************************/
+
+EXTERN bool lpc17_gpioread(uint16_t pinset);
+
+/************************************************************************************
+ * Name: lpc17_gpioirq
+ *
+ * Description:
+ *   Configure an interrupt for the specified GPIO pin.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+EXTERN void lpc17_gpioirq(uint16_t pinset);
+#else
+#  define lpc17_gpioirq(pinset)
+#endif
+
+/************************************************************************************
+ * Name: lpc17_gpioirqenable
+ *
+ * Description:
+ *   Enable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+EXTERN void lpc17_gpioirqenable(int irq);
+#else
+#  define lpc17_gpioirqenable(irq)
+#endif
+
+/************************************************************************************
+ * Name: lpc17_gpioirqdisable
+ *
+ * Description:
+ *   Disable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+EXTERN void lpc17_gpioirqdisable(int irq);
+#else
+#  define lpc17_gpioirqdisable(irq)
+#endif
+
+/************************************************************************************
+ * Function:  lpc17_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the base address of the provided pinset.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO
+EXTERN int lpc17_dumpgpio(uint32_t pinset, const char *msg);
+#else
+#  define lpc17_dumpgpio(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_INTERNAL_H */
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
index 2153ac093..b56d35a8d 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
@@ -50,12 +50,12 @@
 

 /* Memory Map ***********************************************************************/

 

-#define LPC17_FLASH_BASE    0x00000000 /* -0x1fffffff: On-chip non-volatilenmemory */

+#define LPC17_FLASH_BASE    0x00000000 /* -0x1fffffff: On-chip non-volatile memory */

 #define LPC17_SRAM_BASE     0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */

 #define LPC17_ROM_BASE      0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */

 #define LPC17_AHBSRAM_BASE  0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */

 #  define LPC17_SRAM_BANK0  0x20070000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */

-#  define LPC17_SRAM_BANK1  0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank0 (devices 64Kb) */

+#  define LPC17_SRAM_BANK1  0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */

 #define LPC17_GPIO_BASE     0x2009c000 /* -0x2009ffff: GPIO */

 #define LPC17_APB_BASE      0x40000000 /* -0x5fffffff: APB Peripherals */

 #  define LPC17_APB0_BASE   0x40000000 /* -0x4007ffff: APB0 Peripherals */

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_start.c b/nuttx/arch/arm/src/lpc17xx/lpc17_start.c
new file mode 100755
index 000000000..427e3a103
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_start.c
@@ -0,0 +1,151 @@
+/****************************************************************************
+ * arch/arm/src/lpc17xx/lpc17_start.c
+ * arch/arm/src/chip/lpc17_start.c
+ *
+ *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "lpc17_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ *   Print a character on the UART to show boot status.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+#  define showprogress(c) up_lowputc(c)
+#else
+#  define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _start
+ *
+ * Description:
+ *   This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+  const uint32_t *src;
+  uint32_t *dest;
+
+  /* Configure the uart so that we can get debug output as soon as possible */
+
+  lpc17_clockconfig();
+  lpc17_lowsetup();
+  showprogress('A');
+
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+   * certain that there are no issues with the state of global variables.
+   */
+
+  for (dest = &_sbss; dest < &_ebss; )
+    {
+      *dest++ = 0;
+    }
+  showprogress('B');
+
+  /* Move the intialized data section from his temporary holding spot in
+   * FLASH into the correct place in SRAM.  The correct place in SRAM is
+   * give by _sdata and _edata.  The temporary location is in FLASH at the
+   * end of all of the other read-only data (.text, .rodata) at _eronly.
+   */
+
+  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
+    {
+      *dest++ = *src++;
+    }
+  showprogress('C');
+
+  /* Perform early serial initialization */
+
+#ifdef CONFIG_USE_EARLYSERIALINIT
+  up_earlyserialinit();
+#endif
+  showprogress('D');
+
+  /* Initialize onboard resources */
+
+  lpc17_boardinitialize();
+  showprogress('E');
+
+  /* Then start NuttX */
+
+  showprogress('\r');
+  showprogress('\n');
+  os_start();
+
+  /* Shouldn't get here */
+
+  for(;;);
+}
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
new file mode 100755
index 000000000..fc69e7dd8
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
@@ -0,0 +1,349 @@
+/************************************************************************************************

+ * arch/arm/src/lpc17xx/lpc17_vectors.S

+ * arch/arm/src/chip/lpc17_vectors.S

+ *

+ *   Copyright (C) 2010 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions

+ * are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright

+ *    notice, this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright

+ *    notice, this list of conditions and the following disclaimer in

+ *    the documentation and/or other materials provided with the

+ *    distribution.

+ * 3. Neither the name NuttX nor the names of its contributors may be

+ *    used to endorse or promote products derived from this software

+ *    without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ ************************************************************************************************/

+

+/************************************************************************************************

+ * Included Files

+ ************************************************************************************************/

+

+#include <nuttx/config.h>

+#include <arch/irq.h>

+

+/************************************************************************************************

+ * Preprocessor Definitions

+ ************************************************************************************************/

+

+/* Memory Map:

+ *

+ * 0x0000:0000 - Beginning of FLASH. Address of vectors

+ * 0x0003:ffff - End of flash

+ * 0x1000:0000 - Start of CPU SRAM and start of .data (_sdata)

+ *             - End of .data (_edata) and start of .bss (_sbss)

+ *             - End of .bss (_ebss) and bottom of idle stack

+ *             - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap. NOTE

+ *               that the ARM uses a decrement before store stack so that the correct initial

+ *               value is the end of the stack + 4;

+ * 0x1000:7fff - End of CPU SRAM and end of heap (1st region)

+ */

+

+#define IDLE_STACK      (_ebss+CONFIG_IDLETHREAD_STACKSIZE)

+#define HEAP_BASE       (_ebss+CONFIG_IDLETHREAD_STACKSIZE)

+

+/* The Cortex-M3 return from interrupt is unusual.  We provide the following special

+ * address to the BX instruction.  The particular value also forces a return to

+ * thread mode and covers state from the main stack point, the MSP (vs. the MSP).

+ */

+

+#define EXC_RETURN      0xfffffff9

+

+/************************************************************************************************

+ * Global Symbols

+ ************************************************************************************************/

+

+	.globl		__start

+

+	.syntax		unified

+	.thumb

+	.file		"lpc17_vectors.S"

+

+/************************************************************************************************

+ * Macros

+ ************************************************************************************************/

+

+/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3

+ * registers on the stack, then branches to an instantantiation of the following

+ * macro.  This macro simply loads the IRQ number into R0, then jumps to the common

+ * IRQ handling logic.

+ */

+

+	.macro	HANDLER, label, irqno

+	.thumb_func

+\label:

+	mov	r0, #\irqno

+	b	lpc17_common

+	.endm

+

+/************************************************************************************************

+ * Vectors

+ ************************************************************************************************/

+

+	.section	.vectors, "ax"

+	.code		16

+	.align		2

+	.globl		lpc17_vectors

+	.type		lpc17_vectors, function

+

+lpc17_vectors:

+

+/* Processor Exceptions */

+

+	.word	IDLE_STACK			/* Vector  0: Reset stack pointer */

+	.word	__start				/* Vector  1: Reset vector */

+	.word	lpc17_nmi			/* Vector  2: Non-Maskable Interrupt (NMI) */

+	.word	lpc17_hardfault		/* Vector  3: Hard fault */

+	.word	lpc17_mpu			/* Vector  4: Memory management (MPU) */

+	.word	lpc17_busfault		/* Vector  5: Bus fault */

+	.word	lpc17_usagefault	/* Vector  6: Usage fault */

+	.word	lpc17_reserved		/* Vector  7: Reserved */

+	.word	lpc17_reserved		/* Vector  8: Reserved */

+	.word	lpc17_reserved		/* Vector  9: Reserved */

+	.word	lpc17_reserved		/* Vector 10: Reserved */

+	.word	lpc17_svcall		/* Vector 11: SVC call */

+	.word	lpc17_dbgmonitor	/* Vector 12: Debug monitor */

+	.word	lpc17_reserved		/* Vector 13: Reserved */

+	.word	lpc17_pendsv		/* Vector 14: Pendable system service request */

+	.word	lpc17_systick		/* Vector 15: System tick */

+

+/* External Interrupts */

+

+	.word	lpc17_wdt		/* Vector 16+0:  Watchdog timer */

+	.word	lpc17_tmr0		/* Vector 16+1:  Timer 0 */

+	.word	lpc17_tmr1		/* Vector 16+2:  Timer 1 */

+	.word	lpc17_tmr2		/* Vector 16+3:  Timer 2 */

+	.word	lpc17_tmr3		/* Vector 16+4:  Timer 3 */

+	.word	lpc17_uart0		/* Vector 16+5:  UART 0 */

+	.word	lpc17_uart1		/* Vector 16+6:  UART 1 */

+	.word	lpc17_uart2		/* Vector 16+7:  UART 2 */

+	.word	lpc17_uart3		/* Vector 16+8:  UART 3 */

+	.word	lpc17_pwm1		/* Vector 16+9:  PWM */

+	.word	lpc17_i2c0		/* Vector 16+10: I2C 0 */

+	.word	lpc17_i2c1		/* Vector 16+11: I2C 1 */

+	.word	lpc17_i2c2		/* Vector 16+12: I2C 2 */

+	.word	lpc17_spif		/* Vector 16+13: SPI */

+	.word	lpc17_ssp0		/* Vector 16+14: SSP 0 */

+	.word	lpc17_ssp1		/* Vector 16+15: SSP 1 */

+	.word	lpc17_pll0		/* Vector 16+16: PLL 0 */

+	.word	lpc17_rtc		/* Vector 16+17: Real time clock */

+	.word	lpc17_eint0		/* Vector 16+18: External interrupt 0 */

+	.word	lpc17_eint1		/* Vector 16+19: External interrupt 1 */

+	.word	lpc17_eint2		/* Vector 16+20: External interrupt 2 */

+	.word	lpc17_eint3		/* Vector 16+21: External interrupt 3 */

+	.word	lpc17_adc		/* Vector 16+22: A/D Converter */

+	.word	lpc17_bod		/* Vector 16+23: Brown Out detect */

+	.word	lpc17_usb		/* Vector 16+24: USB */

+	.word	lpc17_can		/* Vector 16+25: CAN */

+	.word	lpc17_gpdma		/* Vector 16+26: GPDMA */

+	.word	lpc17_i2s		/* Vector 16+27: I2S */

+	.word	lpc17_eth		/* Vector 16+28: Ethernet */

+	.word	lpc17_ritint		/* Vector 16+29: Repetitive Interrupt Timer */

+	.word	lpc17_mcpwm		/* Vector 16+30: Motor Control PWM */

+	.word	lpc17_qei		/* Vector 16+31: Quadrature Encoder */

+	.word	lpc17_pll1		/* Vector 16+32: PLL 1 */

+	.word	lpc17_usbact		/* Vector 16+33: USB Activity Interrupt */

+	.word	lpc17_canact		/* Vector 16+34: CAN Activity Interrupt */

+	.size	lpc17_vectors, .-lpc17_vectors

+

+/************************************************************************************************

+ * .text

+ ************************************************************************************************/

+

+	.text

+        .type   handlers, function

+        .thumb_func

+handlers:

+	HANDLER	lpc17_reserved, LPC17_IRQ_RESERVED	/* Unexpected/reserved vector */

+	HANDLER lpc17_nmi, LPC17_IRQ_NMI		/* Vector  2: Non-Maskable Interrupt (NMI) */

+	HANDLER lpc17_hardfault, LPC17_IRQ_HARDFAULT	/* Vector  3: Hard fault */

+	HANDLER lpc17_mpu, LPC17_IRQ_MPU		/* Vector  4: Memory management (MPU) */

+	HANDLER lpc17_busfault, LPC17_IRQ_BUSFAULT	/* Vector  5: Bus fault */

+	HANDLER lpc17_usagefault, LPC17_IRQ_USAGEFAULT	/* Vector  6: Usage fault */

+	HANDLER lpc17_svcall, LPC17_IRQ_SVCALL		/* Vector 11: SVC call */

+	HANDLER lpc17_dbgmonitor, LPC17_IRQ_DBGMONITOR	/* Vector 12: Debug Monitor */

+	HANDLER lpc17_pendsv, LPC17_IRQ_PENDSV		/* Vector 14: Penable system service request */

+	HANDLER lpc17_systick, LPC17_IRQ_SYSTICK	/* Vector 15: System tick */

+

+	HANDLER lpc17_wdt, LPC17_IRQ_WDT		/* Vector 16+0:  Watchdog timer */

+	HANDLER lpc17_tmr0, LPC17_IRQ_TMR0		/* Vector 16+1:  Timer 0 */

+	HANDLER lpc17_tmr1, LPC17_IRQ_TMR1 		/* Vector 16+2:  Timer 1 */

+	HANDLER lpc17_tmr2, LPC17_IRQ_TMR2 		/* Vector 16+3:  Timer 2 */

+	HANDLER lpc17_tmr3, LPC17_IRQ_TMR3 		/* Vector 16+4:  Timer 3 */

+	HANDLER lpc17_uart0, LPC17_IRQ_UART0 		/* Vector 16+5:  UART 0 */

+	HANDLER lpc17_uart1, LPC17_IRQ_UART1		/* Vector 16+6:  UART 1 */

+	HANDLER lpc17_uart2, LPC17_IRQ_UART2		/* Vector 16+7:  UART 2 */

+	HANDLER lpc17_uart3, LPC17_IRQ_UART3		/* Vector 16+8:  UART 3 */

+	HANDLER lpc17_pwm1, LPC17_IRQ_PWM1		/* Vector 16+9:  PWM 1 */

+	HANDLER lpc17_i2c0, LPC17_IRQ_I2C0		/* Vector 16+10: I2C 0 */

+	HANDLER lpc17_i2c1, LPC17_IRQ_I2C1		/* Vector 16+11: I2C 1 */

+	HANDLER lpc17_i2c2, LPC17_IRQ_I2C2 		/* Vector 16+12: I2C 2 */

+	HANDLER lpc17_spif, LPC17_IRQ_SPIF		/* Vector 16+13: SPI */

+	HANDLER lpc17_ssp0, LPC17_IRQ_SSP0		/* Vector 16+14: SSP 0 */

+	HANDLER lpc17_ssp1, LPC17_IRQ_SSP1 		/* Vector 16+15: SSP 1 */

+	HANDLER lpc17_pll0, LPC17_IRQ_PLL0		/* Vector 16+16: PLL 0 */

+	HANDLER lpc17_rtc, LPC17_IRQ_RTC		/* Vector 16+17: Real time clock */

+	HANDLER lpc17_eint0, LPC17_IRQ_EINT0		/* Vector 16+18: External interrupt 0 */

+	HANDLER lpc17_eint1, LPC17_IRQ_EINT1		/* Vector 16+19: External interrupt 1 */

+	HANDLER lpc17_eint2, LPC17_IRQ_EINT2 		/* Vector 16+20: External interrupt 2 */

+	HANDLER lpc17_eint3, LPC17_IRQ_EINT3		/* Vector 16+21: External interrupt 3 */

+	HANDLER lpc17_adc, LPC17_IRQ_ADC 		/* Vector 16+22: A/D Converter */

+	HANDLER lpc17_bod, LPC17_IRQ_BOD		/* Vector 16+23: Brown Out detect */

+	HANDLER lpc17_usb, LPC17_IRQ_USB		/* Vector 16+24: USB */

+	HANDLER lpc17_can, LPC17_IRQ_CAN		/* Vector 16+25: CAN */

+	HANDLER lpc17_gpdma, LPC17_IRQ_GPDMA		/* Vector 16+26: GPDMA */

+	HANDLER lpc17_i2s, LPC17_IRQ_I2S		/* Vector 16+27: I2S */

+	HANDLER lpc17_eth, LPC17_IRQ_ETH		/* Vector 16+28: Ethernet */

+	HANDLER lpc17_ritint, LPC17_IRQ_RITINT		/* Vector 16+29: Repetitive Interrupt Timer */

+	HANDLER lpc17_mcpwm, LPC17_IRQ_MCPWM 		/* Vector 16+30: Motor Control PWM */

+	HANDLER lpc17_qei, LPC17_IRQ_QEI 		/* Vector 16+31: Quadrature Encoder */

+	HANDLER lpc17_pll1, LPC17_IRQ_PLL1		/* Vector 16+32: PLL 1 */

+	HANDLER lpc17_usbact, LPC17_IRQ_USBACT		/* Vector 16+33: USB Activity Interrupt */

+	HANDLER lpc17_canact, LPC17_IRQ_CANACT  	/* Vector 16+34: CAN Activity Interrupt */

+

+/* Common IRQ handling logic.  On entry here, the stack is like the following:

+ *

+ *      REG_XPSR

+ *      REG_R15

+ *      REG_R14

+ *      REG_R12

+ *      REG_R3

+ *      REG_R2

+ *      REG_R1

+ * MSP->REG_R0

+ *

+ * and R0 contains the IRQ number

+ */

+

+lpc17_common:

+

+	/* Complete the context save */

+

+	mrs		r1, msp					/* R1=The main stack pointer */

+	mov		r2, r1					/* R2=Copy of the main stack pointer */

+	add		r2, #HW_XCPT_SIZE		/* R2=MSP before the interrupt was taken */

+	mrs		r3, primask				/* R3=Current PRIMASK setting */

+	stmdb	r1!, {r2-r11}			/* Save the remaining registers plus the SP value */

+

+	/* Disable interrupts, select the stack to use for interrupt handling

+	 * and call up_doirq to handle the interrupt

+	 */

+

+	cpsid	i						/* Disable further interrupts */

+

+	/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt

+	 * stack pointer.  The way that this is done here prohibits nested interrupts!

+	 * Otherwise, we will re-use the main stack for interrupt level processing.

+	 */

+

+#ifdef CONFIG_ARCH_INTERRUPTSTACK

+	ld		sp, #up_interruptstack_base

+	str		r1, [sp, #-4]!			/* Save the MSP on the interrupt stack */

+	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */

+	ldr		r1, [sp, #+4]!			/* Recover R1=main stack pointer */

+#else

+	mov		sp, r1					/* We are using the main stack pointer */

+	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */

+	mov		r1, sp					/* Recover R1=main stack pointer */

+#endif

+

+	/* On return from up_doirq, R0 will hold a pointer to register context

+	 * array to use for the interrupt return.  If that return value is the same

+	 * as current stack pointer, then things are relatively easy.

+	 */

+

+	cmp		r0, r1					/* Context switch? */

+	beq		1f						/* Branch if no context switch */

+

+	/* We are returning with a pending context switch.  This case is different

+	 * because in this case, the register save structure does not lie on the

+	 * stack but, rather, are within a TCB structure.  We'll have to copy some

+	 * values to the stack.

+	 */

+

+	add	r1, r0, #SW_XCPT_SIZE		/* R1=Address of HW save area in reg array */

+	ldmia	r1, {r4-r11}			/* Fetch eight registers in HW save area */

+	ldr	r1, [r0, #(4*REG_SP)]		/* R1=Value of SP before interrupt */

+	stmdb	r1!, {r4-r11}			/* Store eight registers in HW save area */

+	ldmia	r0, {r2-r11}			/* Recover R4-R11 + 2 temp values */

+	b		2f						/* Re-join common logic */

+

+	/* We are returning with no context switch.  We simply need to "unwind"

+	 * the same stack frame that we created

+	 */

+1:

+	ldmia	r1!, {r2-r11}			/* Recover R4-R11 + 2 temp values */

+2:

+	msr		msp, r1					/* Recover the return MSP value */

+

+	/* Do we need to restore interrupts? */

+

+	tst		r3, #1					/* PRIMASK bit 1=1 means that interrupts are masked */

+	bne		3f

+	cpsie	i						/* Restore interrupts */

+

+	/* Always return with R14 containing the special value that will: (1)

+	 * return to thread mode, and (2) continue to use the MSP

+	 */

+3:

+	ldr		r14, =EXC_RETURN		/* Load the special value */

+	bx		r14						/* And return */

+	.size	handlers, .-handlers

+

+/************************************************************************************************

+ *  Name: up_interruptstack/g_userstack

+ *

+ * Description:

+ *   Shouldn't happen

+ *

+ ************************************************************************************************/

+

+#if CONFIG_ARCH_INTERRUPTSTACK > 3

+        .bss

+        .align  4

+up_interruptstack:

+        .skip   (CONFIG_ARCH_INTERRUPTSTACK & ~3)

+up_interruptstack_base:

+        .size   up_interruptstack, .-up_interruptstack

+#endif

+

+/************************************************************************************************

+ * .rodata

+ ************************************************************************************************/

+

+	.section	.rodata, "a"

+

+/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end

+ * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS

+ * and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE thread is the thread that

+ * the system boots on and, eventually, becomes the idle, do nothing task that runs

+ * only when there is nothing else to run.  The heap continues from there until the

+ * end of memory.  See g_heapbase below.

+ */

+

+        .globl  g_heapbase

+        .type   g_heapbase, object

+g_heapbase:

+        .word   HEAP_BASE

+        .size   g_heapbase, .-g_heapbase

+

+        .end