Add PHY setup for STM3240G-EVAL Ethernet driver

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4151 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 102 insertions, 5 deletions

diff --git a/nuttx/configs/stm3240g-eval/README.txt b/nuttx/configs/stm3240g-eval/README.txt
index 2cd5339e4..25ee3ce34 100755
--- a/nuttx/configs/stm3240g-eval/README.txt
+++ b/nuttx/configs/stm3240g-eval/README.txt
@@ -374,10 +374,29 @@ STM3240G-EVAL-specific Configuration Options
 	CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode.  Default:
 	  4-bit transfer mode.
 
+	CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
 	CONFIG_STM32_MII - Support Ethernet MII interface
 	CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
 	CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
 	CONFIG_STM32_RMII - Support Ethernet RMII interface
+	CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
+	CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
+	  may be defined to select full duplex mode. Default: half-duplex
+	CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
+	  may be defined to select 100 MBps speed.  Default: 10 Mbps
+	CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  The PHY status register address may diff from PHY to PHY.  This
+	  configuration sets the address of the PHY status register.
+	CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  This provides bit mask indicating 10 or 100MBps speed.
+	CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  This provides the value of the speed bit(s) indicating 100MBps speed.
+	CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  This provide bit mask indicating full or half duplex modes.
+	CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  This provides the value of the mode bits indicating full duplex mode.
+	CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP).  Not supported
+	  but some hooks are indicated with this condition.
 
   STM3240G-EVAL LCD Hardware Configuration
 
diff --git a/nuttx/configs/stm3240g-eval/include/board.h b/nuttx/configs/stm3240g-eval/include/board.h
index 1a1c6738f..663ad7eda 100755
--- a/nuttx/configs/stm3240g-eval/include/board.h
+++ b/nuttx/configs/stm3240g-eval/include/board.h
@@ -172,8 +172,26 @@
 #  define SDIO_SDXFR_CLKDIV     (3 << SDIO_CLKCR_CLKDIV_SHIFT)
 #endif
 
-/* LED definitions ******************************************************************/
+/* Ethernet *************************************************************************/
+/* We need to provide clocking to the MII PHY via MCO1 (PA8) */
+
+#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC)
+
+#  if !defined(CONFIG_STM32_MII)
+#    warning "CONFIG_STM32_MII required for Ethernet"
+#  elif !defined(CONFIG_STM32_MII_MCO1)
+#    warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII"
+#  else
+
+  /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */
+
+#    define BOARD_CFGR_MC01_SOURCE  RCC_CFGR_MCO1_HSE
+#    define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE
 
+#  endif
+#endif
+
+/* LED definitions ******************************************************************/
 /* The STM3240G-EVAL board has 4 LEDs that we will encode as: */
 
 #define LED_STARTED       0  /* LED1 */
@@ -185,6 +203,7 @@
 #define LED_ASSERTION     6  /* LED1 + LED2 + LED3 */
 #define LED_PANIC         7  /* N/C  + N/C  + N/C + LED4 */
 
+/* Button definitions ***************************************************************/
 /* The STM3240G-EVAL supports three buttons: */
 
 #define BUTTON_WAKEUP      0
@@ -200,6 +219,7 @@
 /* Alternate function pin selections ************************************************/
 
 /* UART3:
+ *
  * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open)
  * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX
  */
diff --git a/nuttx/configs/stm3240g-eval/nsh/defconfig b/nuttx/configs/stm3240g-eval/nsh/defconfig
index 490b32a7b..ce69e0295 100755
--- a/nuttx/configs/stm3240g-eval/nsh/defconfig
+++ b/nuttx/configs/stm3240g-eval/nsh/defconfig
@@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y
 #
 # STM32F40xxx Ethernet device driver settings
 #
+# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
 # CONFIG_STM32_MII - Support Ethernet MII interface
 # CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
 # CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
 # CONFIG_STM32_RMII - Support Ethernet RMII interface
-#
+# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
+# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
+#   may be defined to select full duplex mode. Default: half-duplex
+# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
+#   may be defined to select 100 MBps speed.  Default: 10 Mbps
+# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  The PHY status register address may diff from PHY to PHY.  This
+#   configuration sets the address of the PHY status register.
+# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  This provides bit mask indicating 10 or 100MBps speed.
+# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  This provides the value of the speed bit(s) indicating 100MBps speed.
+# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  This provide bit mask indicating full or half duplex modes.
+# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  This provides the value of the mode bits indicating full duplex mode.
+# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP).  Not supported
+#   but some hooks are indicated with this condition.
+#
+CONFIG_STM32_PHYADDR=0x01
 CONFIG_STM32_MII=y
 CONFIG_STM32_MII_MCO1=y
 CONFIG_STM32_MII_MCO2=n
 CONFIG_STM32_RMII=n
+CONFIG_STM32_AUTONEG=y
+#CONFIG_STM32_ETHFD
+#CONFIG_STM32_ETH100MB
+CONFIG_STM32_PHYSR=16
+CONFIG_STM32_PHYSR_SPEED=0x0002
+CONFIG_STM32_PHYSR_100MBPS=0x0000
+CONFIG_STM32_PHYSR_MODE=0x0004
+CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
+CONFIG_STM32_ETH_PTP=n
 
 #
 # General build options
@@ -684,7 +713,7 @@ CONFIG_NET=n
 CONFIG_NET_IPv6=n
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_NET_SOCKOPTS=y
-CONFIG_NET_BUFSIZE=420
+CONFIG_NET_BUFSIZE=562
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_CONNS=40
 CONFIG_NET_MAX_LISTENPORTS=40
diff --git a/nuttx/configs/stm3240g-eval/ostest/defconfig b/nuttx/configs/stm3240g-eval/ostest/defconfig
index cced8c8f2..cc91d8a53 100755
--- a/nuttx/configs/stm3240g-eval/ostest/defconfig
+++ b/nuttx/configs/stm3240g-eval/ostest/defconfig
@@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y
 #
 # STM32F40xxx Ethernet device driver settings
 #
+# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
 # CONFIG_STM32_MII - Support Ethernet MII interface
 # CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
 # CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
 # CONFIG_STM32_RMII - Support Ethernet RMII interface
-#
+# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
+# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
+#   may be defined to select full duplex mode. Default: half-duplex
+# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
+#   may be defined to select 100 MBps speed.  Default: 10 Mbps
+# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  The PHY status register address may diff from PHY to PHY.  This
+#   configuration sets the address of the PHY status register.
+# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  This provides bit mask indicating 10 or 100MBps speed.
+# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  This provides the value of the speed bit(s) indicating 100MBps speed.
+# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  This provide bit mask indicating full or half duplex modes.
+# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
+#   defined.  This provides the value of the mode bits indicating full duplex mode.
+# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP).  Not supported
+#   but some hooks are indicated with this condition.
+#
+CONFIG_STM32_PHYADDR=0x01
 CONFIG_STM32_MII=y
 CONFIG_STM32_MII_MCO1=y
 CONFIG_STM32_MII_MCO2=n
 CONFIG_STM32_RMII=n
+CONFIG_STM32_AUTONEG=y
+#CONFIG_STM32_ETHFD
+#CONFIG_STM32_ETH100MBPS
+CONFIG_STM32_PHYSR=16
+CONFIG_STM32_PHYSR_SPEED=0x0002
+CONFIG_STM32_PHYSR_100MBPS=0x0000
+CONFIG_STM32_PHYSR_MODE=0x0004
+CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
+CONFIG_STM32_ETH_PTP=n
 
 #
 # General build options
@@ -648,7 +677,7 @@ CONFIG_NET=n
 CONFIG_NET_IPv6=n
 CONFIG_NSOCKET_DESCRIPTORS=0
 CONFIG_NET_SOCKOPTS=y
-CONFIG_NET_BUFSIZE=420
+CONFIG_NET_BUFSIZE=562
 CONFIG_NET_TCP=n
 CONFIG_NET_TCP_CONNS=40
 CONFIG_NET_MAX_LISTENPORTS=40